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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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52b2416ceb
This adds a new vGPU cap info bit VGT_CAPS_HUGE_GTT, which is to detect whether the host supports shadowing of huge gtt pages. If host does support it, remove the page sizes restriction for vGPU. Signed-off-by: Changbin Du <changbin.du@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525770425-5373-1-git-send-email-changbin.du@intel.com
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _I915_PVINFO_H_
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#define _I915_PVINFO_H_
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/* The MMIO offset of the shared info between guest and host emulator */
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#define VGT_PVINFO_PAGE 0x78000
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#define VGT_PVINFO_SIZE 0x1000
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/*
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* The following structure pages are defined in GEN MMIO space
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* for virtualization. (One page for now)
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*/
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#define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */
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#define VGT_VERSION_MAJOR 1
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#define VGT_VERSION_MINOR 0
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/*
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* notifications from guest to vgpu device model
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*/
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enum vgt_g2v_type {
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VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
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VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
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VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
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VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
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VGT_G2V_EXECLIST_CONTEXT_CREATE,
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VGT_G2V_EXECLIST_CONTEXT_DESTROY,
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VGT_G2V_MAX,
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};
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/*
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* VGT capabilities type
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*/
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#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
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#define VGT_CAPS_HWSP_EMULATION BIT(3)
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#define VGT_CAPS_HUGE_GTT BIT(4)
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struct vgt_if {
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u64 magic; /* VGT_MAGIC */
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u16 version_major;
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u16 version_minor;
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u32 vgt_id; /* ID of vGT instance */
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u32 vgt_caps; /* VGT capabilities */
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u32 rsv1[11]; /* pad to offset 0x40 */
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/*
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* Data structure to describe the balooning info of resources.
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* Each VM can only have one portion of continuous area for now.
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* (May support scattered resource in future)
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* (starting from offset 0x40)
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*/
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struct {
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/* Aperture register balooning */
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struct {
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u32 base;
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u32 size;
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} mappable_gmadr; /* aperture */
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/* GMADR register balooning */
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struct {
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u32 base;
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u32 size;
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} nonmappable_gmadr; /* non aperture */
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/* allowed fence registers */
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u32 fence_num;
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u32 rsv2[3];
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} avail_rs; /* available/assigned resource */
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u32 rsv3[0x200 - 24]; /* pad to half page */
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/*
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* The bottom half page is for response from Gfx driver to hypervisor.
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*/
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u32 rsv4;
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u32 display_ready; /* ready for display owner switch */
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u32 rsv5[4];
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u32 g2v_notify;
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u32 rsv6[7];
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struct {
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u32 lo;
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u32 hi;
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} pdp[4];
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u32 execlist_context_descriptor_lo;
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u32 execlist_context_descriptor_hi;
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u32 rsv7[0x200 - 24]; /* pad to one page */
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} __packed;
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#define vgtif_reg(x) \
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_MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))
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/* vGPU display status to be used by the host side */
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#define VGT_DRV_DISPLAY_NOT_READY 0
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#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
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#endif /* _I915_PVINFO_H_ */
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