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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d702419134
Certain users can not use right now the DMAengine API due to missing
features in the core. Prime example is Networking.
These users can use the glue layer interface to avoid misuse of DMAengine
API and when the core gains the needed features they can be converted to
use generic API.
The most prominent features the glue layer clients are depending on:
- most PSI-L native peripheral use extra rflow ranges on a receive channel
and depending on the peripheral's configuration packets from a single
free descriptor ring is going to be received to different receive ring
- it is also possible to have different free descriptor rings per rflow
and an rflow can also support 4 additional free descriptor ring based
on the size of the incoming packet
- out of order completion of descriptors on a channel
- when we have several queues to handle different priority packets the
descriptors will be completed 'out-of-order'
- the notion of prep_slave_sg is not matching with what the streaming type
of operation is demanding for networking
- Streaming type of operation
- Ability to fill the free descriptor ring with descriptors in
anticipation of incoming traffic and when a packet arrives UDMAP will
form a packet and gives it to the client driver
- the descriptors are not backed with exact size data buffers as we don't
know the size of the packet we will receive, but as a generic pool of
buffers to be used by the receive channel
- NAPI type of operation (polling instead of interrupt driven transfer)
- without this we can not sustain gigabit speeds and we need to support NAPI
- not to limit this to networking, but other high performance operations
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20191223110458.30766-12-peter.ujfalusi@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
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{
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return navss_psil_pair(ud, src_thread, dst_thread);
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}
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EXPORT_SYMBOL(xudma_navss_psil_pair);
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int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
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{
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return navss_psil_unpair(ud, src_thread, dst_thread);
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}
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EXPORT_SYMBOL(xudma_navss_psil_unpair);
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struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property)
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{
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struct device_node *udma_node = np;
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struct platform_device *pdev;
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struct udma_dev *ud;
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if (property) {
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udma_node = of_parse_phandle(np, property, 0);
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if (!udma_node) {
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pr_err("UDMA node is not found\n");
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return ERR_PTR(-ENODEV);
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}
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}
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pdev = of_find_device_by_node(udma_node);
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if (!pdev) {
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pr_debug("UDMA device not found\n");
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return ERR_PTR(-EPROBE_DEFER);
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}
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if (np != udma_node)
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of_node_put(udma_node);
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ud = platform_get_drvdata(pdev);
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if (!ud) {
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pr_debug("UDMA has not been probed\n");
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return ERR_PTR(-EPROBE_DEFER);
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}
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return ud;
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}
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EXPORT_SYMBOL(of_xudma_dev_get);
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u32 xudma_dev_get_psil_base(struct udma_dev *ud)
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{
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return ud->psil_base;
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}
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EXPORT_SYMBOL(xudma_dev_get_psil_base);
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struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud)
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{
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return &ud->tisci_rm;
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}
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EXPORT_SYMBOL(xudma_dev_get_tisci_rm);
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int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt)
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{
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return __udma_alloc_gp_rflow_range(ud, from, cnt);
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}
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EXPORT_SYMBOL(xudma_alloc_gp_rflow_range);
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int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt)
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{
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return __udma_free_gp_rflow_range(ud, from, cnt);
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}
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EXPORT_SYMBOL(xudma_free_gp_rflow_range);
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bool xudma_rflow_is_gp(struct udma_dev *ud, int id)
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{
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return !test_bit(id, ud->rflow_gp_map);
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}
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EXPORT_SYMBOL(xudma_rflow_is_gp);
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#define XUDMA_GET_PUT_RESOURCE(res) \
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struct udma_##res *xudma_##res##_get(struct udma_dev *ud, int id) \
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{ \
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return __udma_reserve_##res(ud, false, id); \
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} \
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EXPORT_SYMBOL(xudma_##res##_get); \
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\
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void xudma_##res##_put(struct udma_dev *ud, struct udma_##res *p) \
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{ \
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clear_bit(p->id, ud->res##_map); \
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} \
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EXPORT_SYMBOL(xudma_##res##_put)
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XUDMA_GET_PUT_RESOURCE(tchan);
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XUDMA_GET_PUT_RESOURCE(rchan);
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struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id)
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{
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return __udma_get_rflow(ud, id);
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}
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EXPORT_SYMBOL(xudma_rflow_get);
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void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p)
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{
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__udma_put_rflow(ud, p);
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}
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EXPORT_SYMBOL(xudma_rflow_put);
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#define XUDMA_GET_RESOURCE_ID(res) \
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int xudma_##res##_get_id(struct udma_##res *p) \
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{ \
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return p->id; \
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} \
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EXPORT_SYMBOL(xudma_##res##_get_id)
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XUDMA_GET_RESOURCE_ID(tchan);
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XUDMA_GET_RESOURCE_ID(rchan);
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XUDMA_GET_RESOURCE_ID(rflow);
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/* Exported register access functions */
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#define XUDMA_RT_IO_FUNCTIONS(res) \
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u32 xudma_##res##rt_read(struct udma_##res *p, int reg) \
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{ \
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return udma_##res##rt_read(p, reg); \
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} \
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EXPORT_SYMBOL(xudma_##res##rt_read); \
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\
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void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \
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{ \
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udma_##res##rt_write(p, reg, val); \
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} \
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EXPORT_SYMBOL(xudma_##res##rt_write)
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XUDMA_RT_IO_FUNCTIONS(tchan);
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XUDMA_RT_IO_FUNCTIONS(rchan);
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