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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ac5ced91aa
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the LPC32xx SoC, adjusting the compatible strings, adding interrupts and status configuration. On the PHY3250 reference board, UART2 is enabled. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
186 lines
3.3 KiB
Plaintext
186 lines
3.3 KiB
Plaintext
/*
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* PHYTEC phyCORE-LPC3250 board
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*
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "lpc32xx.dtsi"
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/ {
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model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
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compatible = "phytec,phy3250", "nxp,lpc3250";
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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device_type = "memory";
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reg = <0 0x4000000>;
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};
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ahb {
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mac: ethernet@31060000 {
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phy-mode = "rmii";
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use-iram;
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};
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/* Here, choose exactly one from: ohci, usbd */
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ohci@31020000 {
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transceiver = <&isp1301>;
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status = "okay";
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};
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/*
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usbd@31020000 {
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transceiver = <&isp1301>;
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status = "okay";
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};
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*/
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clcd@31040000 {
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status = "okay";
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};
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/* 64MB Flash via SLC NAND controller */
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slc: flash@20020000 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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nxp,wdr-clks = <14>;
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nxp,wwidth = <40000000>;
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nxp,whold = <100000000>;
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nxp,wsetup = <100000000>;
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nxp,rdr-clks = <14>;
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nxp,rwidth = <40000000>;
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nxp,rhold = <66666666>;
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nxp,rsetup = <100000000>;
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nand-on-flash-bbt;
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gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
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mtd0@00000000 {
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label = "phy3250-boot";
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reg = <0x00000000 0x00064000>;
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read-only;
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};
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mtd1@00064000 {
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label = "phy3250-uboot";
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reg = <0x00064000 0x00190000>;
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read-only;
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};
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mtd2@001f4000 {
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label = "phy3250-ubt-prms";
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reg = <0x001f4000 0x00010000>;
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};
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mtd3@00204000 {
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label = "phy3250-kernel";
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reg = <0x00204000 0x00400000>;
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};
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mtd4@00604000 {
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label = "phy3250-rootfs";
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reg = <0x00604000 0x039fc000>;
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};
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};
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apb {
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uart5: serial@40090000 {
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status = "okay";
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};
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uart3: serial@40080000 {
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status = "okay";
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};
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i2c1: i2c@400A0000 {
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clock-frequency = <100000>;
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pcf8563: rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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uda1380: uda1380@18 {
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compatible = "nxp,uda1380";
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reg = <0x18>;
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power-gpio = <&gpio 0x59 0>;
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reset-gpio = <&gpio 0x51 0>;
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dac-clk = "wspll";
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};
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};
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i2c2: i2c@400A8000 {
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clock-frequency = <100000>;
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};
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i2cusb: i2c@31020300 {
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clock-frequency = <100000>;
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isp1301: usb-transceiver@2c {
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compatible = "nxp,isp1301";
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reg = <0x2c>;
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};
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};
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ssp0: ssp@20084000 {
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eeprom: at25@0 {
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compatible = "atmel,at25";
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};
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};
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sd@20098000 {
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wp-gpios = <&gpio 3 0 0>;
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cd-gpios = <&gpio 3 1 0>;
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cd-inverted;
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bus-width = <4>;
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status = "okay";
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};
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};
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fab {
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uart2: serial@40018000 {
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status = "okay";
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};
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tsc@40048000 {
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status = "okay";
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};
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key@40050000 {
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status = "okay";
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keypad,num-rows = <1>;
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keypad,num-columns = <1>;
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nxp,debounce-delay-ms = <3>;
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nxp,scan-delay-ms = <34>;
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linux,keymap = <0x00000002>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led0 {
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gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
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linux,default-trigger = "heartbeat";
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default-state = "off";
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};
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led1 {
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gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
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linux,default-trigger = "timer";
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default-state = "off";
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};
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};
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};
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