mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
f2f98c1d7f
Since the referenced commit, Ethernet fails to come up at boot on the
board meson-gxl-s905x-libretech-cc. Fix this by re-enabling the
genphy_soft_reset callback for the Amlogic Meson GXL PHY driver.
Fixes: 6e2d85ec05 ("net: phy: Stop with excessive soft reset")
Signed-off-by: Timotej Lazar <timotej.lazar@araneo.si>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
261 lines
6.8 KiB
C
261 lines
6.8 KiB
C
/*
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* Amlogic Meson GXL Internal PHY Driver
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2016 BayLibre, SAS. All rights reserved.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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#define TSTCNTL 20
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#define TSTCNTL_READ BIT(15)
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#define TSTCNTL_WRITE BIT(14)
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#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)
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#define TSTCNTL_TEST_MODE BIT(10)
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#define TSTCNTL_READ_ADDRESS GENMASK(9, 5)
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#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
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#define TSTREAD1 21
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#define TSTWRITE 23
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#define INTSRC_FLAG 29
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#define INTSRC_ANEG_PR BIT(1)
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#define INTSRC_PARALLEL_FAULT BIT(2)
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#define INTSRC_ANEG_LP_ACK BIT(3)
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#define INTSRC_LINK_DOWN BIT(4)
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#define INTSRC_REMOTE_FAULT BIT(5)
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#define INTSRC_ANEG_COMPLETE BIT(6)
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#define INTSRC_MASK 30
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#define BANK_ANALOG_DSP 0
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#define BANK_WOL 1
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#define BANK_BIST 3
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/* WOL Registers */
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#define LPI_STATUS 0xc
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#define LPI_STATUS_RSV12 BIT(12)
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/* BIST Registers */
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#define FR_PLL_CONTROL 0x1b
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#define FR_PLL_DIV0 0x1c
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#define FR_PLL_DIV1 0x1d
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static int meson_gxl_open_banks(struct phy_device *phydev)
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{
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int ret;
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/* Enable Analog and DSP register Bank access by
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* toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register
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*/
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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}
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static void meson_gxl_close_banks(struct phy_device *phydev)
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{
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phy_write(phydev, TSTCNTL, 0);
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}
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static int meson_gxl_read_reg(struct phy_device *phydev,
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unsigned int bank, unsigned int reg)
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{
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int ret;
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ret = meson_gxl_open_banks(phydev);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ |
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FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
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TSTCNTL_TEST_MODE |
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FIELD_PREP(TSTCNTL_READ_ADDRESS, reg));
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if (ret)
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goto out;
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ret = phy_read(phydev, TSTREAD1);
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out:
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/* Close the bank access on our way out */
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meson_gxl_close_banks(phydev);
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return ret;
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}
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static int meson_gxl_write_reg(struct phy_device *phydev,
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unsigned int bank, unsigned int reg,
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uint16_t value)
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{
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int ret;
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ret = meson_gxl_open_banks(phydev);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTWRITE, value);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE |
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FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
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TSTCNTL_TEST_MODE |
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FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg));
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out:
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/* Close the bank access on our way out */
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meson_gxl_close_banks(phydev);
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return ret;
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}
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Enable fractional PLL */
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa);
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if (ret)
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return ret;
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return genphy_config_init(phydev);
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}
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/* This function is provided to cope with the possible failures of this phy
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* during aneg process. When aneg fails, the PHY reports that aneg is done
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* but the value found in MII_LPA is wrong:
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* - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
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* the link partner (LP) supports aneg but the LP never acked our base
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* code word, it is likely that we never sent it to begin with.
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* - Late failures: MII_LPA is filled with a value which seems to make sense
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* but it actually is not what the LP is advertising. It seems that we
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* can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
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* If this particular bit is not set when aneg is reported being done,
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* it means MII_LPA is likely to be wrong.
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*
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* In both case, forcing a restart of the aneg process solve the problem.
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* When this failure happens, the first retry is usually successful but,
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* in some cases, it may take up to 6 retries to get a decent result
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*/
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static int meson_gxl_read_status(struct phy_device *phydev)
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{
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int ret, wol, lpa, exp;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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ret = genphy_aneg_done(phydev);
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if (ret < 0)
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return ret;
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else if (!ret)
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goto read_status_continue;
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/* Aneg is done, let's check everything is fine */
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wol = meson_gxl_read_reg(phydev, BANK_WOL, LPI_STATUS);
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if (wol < 0)
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return wol;
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lpa = phy_read(phydev, MII_LPA);
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if (lpa < 0)
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return lpa;
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exp = phy_read(phydev, MII_EXPANSION);
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if (exp < 0)
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return exp;
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if (!(wol & LPI_STATUS_RSV12) ||
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((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
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/* Looks like aneg failed after all */
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phydev_dbg(phydev, "LPA corruption - aneg restart\n");
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return genphy_restart_aneg(phydev);
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}
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}
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read_status_continue:
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return genphy_read_status(phydev);
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}
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static int meson_gxl_ack_interrupt(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, INTSRC_FLAG);
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return ret < 0 ? ret : 0;
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}
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static int meson_gxl_config_intr(struct phy_device *phydev)
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{
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u16 val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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val = INTSRC_ANEG_PR
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| INTSRC_PARALLEL_FAULT
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| INTSRC_ANEG_LP_ACK
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| INTSRC_LINK_DOWN
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| INTSRC_REMOTE_FAULT
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| INTSRC_ANEG_COMPLETE;
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} else {
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val = 0;
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}
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return phy_write(phydev, INTSRC_MASK, val);
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}
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static struct phy_driver meson_gxl_phy[] = {
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{
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.phy_id = 0x01814400,
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.phy_id_mask = 0xfffffff0,
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.name = "Meson GXL Internal PHY",
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_IS_INTERNAL,
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.soft_reset = genphy_soft_reset,
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.config_init = meson_gxl_config_init,
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.aneg_done = genphy_aneg_done,
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.read_status = meson_gxl_read_status,
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.ack_interrupt = meson_gxl_ack_interrupt,
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.config_intr = meson_gxl_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
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{ 0x01814400, 0xfffffff0 },
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{ }
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};
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module_phy_driver(meson_gxl_phy);
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MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
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MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
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MODULE_AUTHOR("Baoqi wang");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL");
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