mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
57527f8d4d
2484 Mhz (Japan) usage requires filter coefficients to be programmed in the CCK TX FIR registers. This is required for AR9331, AR9485 and AR9462. Fix this and also remove a few useless macros and a duplicate variable. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
685 lines
20 KiB
C
685 lines
20 KiB
C
/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "ar9003_mac.h"
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#include "ar9003_2p2_initvals.h"
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#include "ar9485_initvals.h"
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#include "ar9340_initvals.h"
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#include "ar9330_1p1_initvals.h"
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#include "ar9330_1p2_initvals.h"
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#include "ar955x_1p0_initvals.h"
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#include "ar9580_1p0_initvals.h"
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#include "ar9462_2p0_initvals.h"
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#include "ar9565_1p0_initvals.h"
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/* General hardware code for the AR9003 hadware family */
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/*
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* The AR9003 family uses a new INI format (pre, core, post
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* arrays per subsystem). This provides support for the
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* AR9003 2.2 chipsets.
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*/
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static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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{
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if (AR_SREV_9330_11(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9331_1p1_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9331_1p1_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9331_1p1_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9331_1p1_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9331_1p1_radio_core);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9331_1p1_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9331_1p1_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9331_common_rx_gain_1p1);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9331_modes_lowest_ob_db_tx_gain_1p1);
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/* Japan 2484 Mhz CCK */
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p1_xtal_25M);
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else
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p1_xtal_40M);
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} else if (AR_SREV_9330_12(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9331_1p2_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9331_1p2_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9331_1p2_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9331_1p2_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9331_1p2_radio_core);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9331_1p2_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9331_1p2_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9331_common_rx_gain_1p2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9331_modes_lowest_ob_db_tx_gain_1p2);
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/* Japan 2484 Mhz CCK */
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p2_xtal_25M);
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else
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p2_xtal_40M);
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} else if (AR_SREV_9340(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9340_1p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9340_1p0_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9340_1p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9340_1p0_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9340_1p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9340_1p0_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9340_1p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9340_1p0_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9340Common_wo_xlna_rx_gain_table_1p0);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9340Modes_high_ob_db_tx_gain_table_1p0);
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9340Modes_fast_clock_1p0);
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if (!ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9340_1p0_radio_core_40M);
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} else if (AR_SREV_9485_11(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9485_1_1_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9485_1_1_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9485_1_1_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9485_1_1_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9485_1_1_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9485_1_1_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9485_1_1_soc_preamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9485Common_wo_xlna_rx_gain_1_1);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9485_modes_lowest_ob_db_tx_gain_1_1);
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/* Japan 2484 Mhz CCK */
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9485_1_1_pcie_phy_clkreq_disable_L1);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9485_1_1_pcie_phy_clkreq_disable_L1);
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} else if (AR_SREV_9462_20(ah)) {
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9462_2p0_mac_postamble);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9462_2p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9462_2p0_baseband_postamble);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9462_2p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9462_2p0_radio_postamble);
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INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
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ar9462_2p0_radio_postamble_sys2ant);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9462_2p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9462_2p0_soc_postamble);
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9462_common_rx_gain_table_2p0);
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/* Awake -> Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9462_pciephy_clkreq_disable_L1_2p0);
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/* Sleep -> Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9462_pciephy_clkreq_disable_L1_2p0);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9462_modes_fast_clock_2p0);
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
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} else if (AR_SREV_9550(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar955x_1p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar955x_1p0_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar955x_1p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar955x_1p0_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar955x_1p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar955x_1p0_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar955x_1p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar955x_1p0_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar955x_1p0_common_wo_xlna_rx_gain_table);
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INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
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ar955x_1p0_common_wo_xlna_rx_gain_bounds);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar955x_1p0_modes_xpa_tx_gain_table);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar955x_1p0_modes_fast_clock);
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} else if (AR_SREV_9580(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9580_1p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9580_1p0_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9580_1p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9580_1p0_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9580_1p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9580_1p0_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9580_1p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9580_1p0_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9580_1p0_rx_gain_table);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_low_ob_db_tx_gain_table);
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9580_1p0_modes_fast_clock);
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} else if (AR_SREV_9565(ah)) {
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9565_1p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9565_1p0_mac_postamble);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9565_1p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9565_1p0_baseband_postamble);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9565_1p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9565_1p0_radio_postamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9565_1p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9565_1p0_soc_postamble);
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9565_1p0_Common_rx_gain_table);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9565_1p0_pciephy_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9565_1p0_pciephy_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9565_1p0_modes_fast_clock);
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} else {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9300_2p2_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9300_2p2_mac_postamble);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9300_2p2_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9300_2p2_baseband_postamble);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9300_2p2_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9300_2p2_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9300_2p2_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9300_2p2_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9300Modes_fast_clock_2p2);
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}
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}
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static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
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{
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if (AR_SREV_9330_12(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9331_modes_lowest_ob_db_tx_gain_1p2);
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else if (AR_SREV_9330_11(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9331_modes_lowest_ob_db_tx_gain_1p1);
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else if (AR_SREV_9340(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
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else if (AR_SREV_9485_11(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9485_modes_lowest_ob_db_tx_gain_1_1);
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else if (AR_SREV_9550(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar955x_1p0_modes_xpa_tx_gain_table);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_lowest_ob_db_tx_gain_table);
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else if (AR_SREV_9462_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9462_modes_low_ob_db_tx_gain_table_2p0);
|
|
else if (AR_SREV_9565(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9565_1p0_modes_low_ob_db_tx_gain_table);
|
|
else
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
|
|
}
|
|
|
|
static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9330_12(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9331_modes_high_ob_db_tx_gain_1p2);
|
|
else if (AR_SREV_9330_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9331_modes_high_ob_db_tx_gain_1p1);
|
|
else if (AR_SREV_9340(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9340Modes_high_ob_db_tx_gain_table_1p0);
|
|
else if (AR_SREV_9485_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9485Modes_high_ob_db_tx_gain_1_1);
|
|
else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9580_1p0_high_ob_db_tx_gain_table);
|
|
else if (AR_SREV_9550(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar955x_1p0_modes_no_xpa_tx_gain_table);
|
|
else if (AR_SREV_9462_20(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9462_modes_high_ob_db_tx_gain_table_2p0);
|
|
else if (AR_SREV_9565(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9565_1p0_modes_high_ob_db_tx_gain_table);
|
|
else
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9300Modes_high_ob_db_tx_gain_table_2p2);
|
|
}
|
|
|
|
static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9330_12(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9331_modes_low_ob_db_tx_gain_1p2);
|
|
else if (AR_SREV_9330_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9331_modes_low_ob_db_tx_gain_1p1);
|
|
else if (AR_SREV_9340(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9340Modes_low_ob_db_tx_gain_table_1p0);
|
|
else if (AR_SREV_9485_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9485Modes_low_ob_db_tx_gain_1_1);
|
|
else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9580_1p0_low_ob_db_tx_gain_table);
|
|
else if (AR_SREV_9565(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9565_1p0_modes_low_ob_db_tx_gain_table);
|
|
else
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9300Modes_low_ob_db_tx_gain_table_2p2);
|
|
}
|
|
|
|
static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9330_12(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9331_modes_high_power_tx_gain_1p2);
|
|
else if (AR_SREV_9330_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9331_modes_high_power_tx_gain_1p1);
|
|
else if (AR_SREV_9340(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9340Modes_high_power_tx_gain_table_1p0);
|
|
else if (AR_SREV_9485_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9485Modes_high_power_tx_gain_1_1);
|
|
else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9580_1p0_high_power_tx_gain_table);
|
|
else if (AR_SREV_9565(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9565_1p0_modes_high_power_tx_gain_table);
|
|
else
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9300Modes_high_power_tx_gain_table_2p2);
|
|
}
|
|
|
|
static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9340(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
|
|
else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9580_1p0_mixed_ob_db_tx_gain_table);
|
|
}
|
|
|
|
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
|
|
{
|
|
switch (ar9003_hw_get_tx_gain_idx(ah)) {
|
|
case 0:
|
|
default:
|
|
ar9003_tx_gain_table_mode0(ah);
|
|
break;
|
|
case 1:
|
|
ar9003_tx_gain_table_mode1(ah);
|
|
break;
|
|
case 2:
|
|
ar9003_tx_gain_table_mode2(ah);
|
|
break;
|
|
case 3:
|
|
ar9003_tx_gain_table_mode3(ah);
|
|
break;
|
|
case 4:
|
|
ar9003_tx_gain_table_mode4(ah);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9330_12(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9331_common_rx_gain_1p2);
|
|
else if (AR_SREV_9330_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9331_common_rx_gain_1p1);
|
|
else if (AR_SREV_9340(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9340Common_rx_gain_table_1p0);
|
|
else if (AR_SREV_9485_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9485Common_wo_xlna_rx_gain_1_1);
|
|
else if (AR_SREV_9550(ah)) {
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar955x_1p0_common_rx_gain_table);
|
|
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
|
ar955x_1p0_common_rx_gain_bounds);
|
|
} else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9580_1p0_rx_gain_table);
|
|
else if (AR_SREV_9462_20(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9462_common_rx_gain_table_2p0);
|
|
else
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9300Common_rx_gain_table_2p2);
|
|
}
|
|
|
|
static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9330_12(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9331_common_wo_xlna_rx_gain_1p2);
|
|
else if (AR_SREV_9330_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9331_common_wo_xlna_rx_gain_1p1);
|
|
else if (AR_SREV_9340(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9340Common_wo_xlna_rx_gain_table_1p0);
|
|
else if (AR_SREV_9485_11(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9485Common_wo_xlna_rx_gain_1_1);
|
|
else if (AR_SREV_9462_20(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9462_common_wo_xlna_rx_gain_table_2p0);
|
|
else if (AR_SREV_9550(ah)) {
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar955x_1p0_common_wo_xlna_rx_gain_table);
|
|
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
|
ar955x_1p0_common_wo_xlna_rx_gain_bounds);
|
|
} else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9580_1p0_wo_xlna_rx_gain_table);
|
|
else if (AR_SREV_9565(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9565_1p0_common_wo_xlna_rx_gain_table);
|
|
else
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9300Common_wo_xlna_rx_gain_table_2p2);
|
|
}
|
|
|
|
static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9462_20(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
ar9462_common_mixed_rx_gain_table_2p0);
|
|
}
|
|
|
|
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
|
|
{
|
|
switch (ar9003_hw_get_rx_gain_idx(ah)) {
|
|
case 0:
|
|
default:
|
|
ar9003_rx_gain_table_mode0(ah);
|
|
break;
|
|
case 1:
|
|
ar9003_rx_gain_table_mode1(ah);
|
|
break;
|
|
case 2:
|
|
ar9003_rx_gain_table_mode2(ah);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* set gain table pointers according to values read from the eeprom */
|
|
static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
|
|
{
|
|
ar9003_tx_gain_table_apply(ah);
|
|
ar9003_rx_gain_table_apply(ah);
|
|
}
|
|
|
|
/*
|
|
* Helper for ASPM support.
|
|
*
|
|
* Disable PLL when in L0s as well as receiver clock when in L1.
|
|
* This power saving option must be enabled through the SerDes.
|
|
*
|
|
* Programming the SerDes must go through the same 288 bit serial shift
|
|
* register as the other analog registers. Hence the 9 writes.
|
|
*/
|
|
static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
|
|
bool power_off)
|
|
{
|
|
/* Nothing to do on restore for 11N */
|
|
if (!power_off /* !restore */) {
|
|
/* set bit 19 to allow forcing of pcie core into L1 state */
|
|
REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
|
|
|
|
/* Several PCIe massages to ensure proper behaviour */
|
|
if (ah->config.pcie_waen)
|
|
REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
|
|
else
|
|
REG_WRITE(ah, AR_WA, ah->WARegVal);
|
|
}
|
|
|
|
/*
|
|
* Configire PCIE after Ini init. SERDES values now come from ini file
|
|
* This enables PCIe low power mode.
|
|
*/
|
|
if (ah->config.pcieSerDesWrite) {
|
|
unsigned int i;
|
|
struct ar5416IniArray *array;
|
|
|
|
array = power_off ? &ah->iniPcieSerdes :
|
|
&ah->iniPcieSerdesLowPower;
|
|
|
|
for (i = 0; i < array->ia_rows; i++) {
|
|
REG_WRITE(ah,
|
|
INI_RA(array, i, 0),
|
|
INI_RA(array, i, 1));
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Sets up the AR9003 hardware familiy callbacks */
|
|
void ar9003_hw_attach_ops(struct ath_hw *ah)
|
|
{
|
|
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
|
|
|
priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
|
|
priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
|
|
|
|
ops->config_pci_powersave = ar9003_hw_configpcipowersave;
|
|
|
|
ar9003_hw_attach_phy_ops(ah);
|
|
ar9003_hw_attach_calib_ops(ah);
|
|
ar9003_hw_attach_mac_ops(ah);
|
|
}
|