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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c620f7bd0b
Mostly just incremental improvements here: - Introduce AT_HWCAP2 for advertising CPU features to userspace - Expose SVE2 availability to userspace - Support for "data cache clean to point of deep persistence" (DC PODP) - Honour "mitigations=off" on the cmdline and advertise status via sysfs - CPU timer erratum workaround (Neoverse-N1 #1188873) - Introduce perf PMU driver for the SMMUv3 performance counters - Add config option to disable the kuser helpers page for AArch32 tasks - Futex modifications to ensure liveness under contention - Rework debug exception handling to seperate kernel and user handlers - Non-critical fixes and cleanup -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAlzMFGgACgkQt6xw3ITB YzTicAf/TX1h1+ecbx4WJAa4qeiOCPoNpG9efldQumqJhKL44MR5bkhuShna5mwE ptm5qUXkZCxLTjzssZKnbdbgwa3t+emW8Of3D91IfI9akiZbMoDx5FGgcNbqjazb RLrhOFHwgontA38yppZN+DrL+sXbvif/CVELdHahkEx6KepSGaS2lmPXRmz/W56v 4yIRy/zxc3Dhjgfm3wKh72nBwoZdLiIc4mchd5pthNlR9E2idrYkQegG1C+gA00r o8uZRVOWgoh7H+QJE+xLUc8PaNCg8xqRRXOuZYg9GOz6hh7zSWhm+f1nRz9S2tIR gIgsCHNqoO2I3E1uJpAQXDGtt2kFhA== =ulpJ -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: "Mostly just incremental improvements here: - Introduce AT_HWCAP2 for advertising CPU features to userspace - Expose SVE2 availability to userspace - Support for "data cache clean to point of deep persistence" (DC PODP) - Honour "mitigations=off" on the cmdline and advertise status via sysfs - CPU timer erratum workaround (Neoverse-N1 #1188873) - Introduce perf PMU driver for the SMMUv3 performance counters - Add config option to disable the kuser helpers page for AArch32 tasks - Futex modifications to ensure liveness under contention - Rework debug exception handling to seperate kernel and user handlers - Non-critical fixes and cleanup" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits) Documentation: Add ARM64 to kernel-parameters.rst arm64/speculation: Support 'mitigations=' cmdline option arm64: ssbs: Don't treat CPUs with SSBS as unaffected by SSB arm64: enable generic CPU vulnerabilites support arm64: add sysfs vulnerability show for speculative store bypass arm64: Fix size of __early_cpu_boot_status clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters clocksource/arm_arch_timer: Remove use of workaround static key clocksource/arm_arch_timer: Drop use of static key in arch_timer_reg_read_stable clocksource/arm_arch_timer: Direcly assign set_next_event workaround arm64: Use arch_timer_read_counter instead of arch_counter_get_cntvct watchdog/sbsa: Use arch_timer_read_counter instead of arch_counter_get_cntvct ARM: vdso: Remove dependency with the arch_timer driver internals arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1 arm64: Add part number for Neoverse N1 arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT arm64: Restrict ARM64_ERRATUM_1188873 mitigation to AArch32 arm64: mm: Remove pte_unmap_nested() arm64: Fix compiler warning from pte_unmap() with -Wunused-but-set-variable arm64: compat: Reduce address limit for 64K pages ...
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/*
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* Based on arch/arm/include/asm/tlb.h
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*
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* Copyright (C) 2002 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_TLB_H
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#define __ASM_TLB_H
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#include <linux/pagemap.h>
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#include <linux/swap.h>
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static inline void __tlb_remove_table(void *_table)
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{
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free_page_and_swap_cache((struct page *)_table);
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}
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#define tlb_flush tlb_flush
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static void tlb_flush(struct mmu_gather *tlb);
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#include <asm-generic/tlb.h>
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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struct vm_area_struct vma = TLB_FLUSH_VMA(tlb->mm, 0);
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bool last_level = !tlb->freed_tables;
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unsigned long stride = tlb_get_unmap_size(tlb);
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/*
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* If we're tearing down the address space then we only care about
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* invalidating the walk-cache, since the ASID allocator won't
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* reallocate our ASID without invalidating the entire TLB.
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*/
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if (tlb->fullmm) {
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if (!last_level)
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flush_tlb_mm(tlb->mm);
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return;
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}
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__flush_tlb_range(&vma, tlb->start, tlb->end, stride, last_level);
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}
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static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
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unsigned long addr)
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{
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pgtable_page_dtor(pte);
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tlb_remove_table(tlb, pte);
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}
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#if CONFIG_PGTABLE_LEVELS > 2
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static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
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unsigned long addr)
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{
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struct page *page = virt_to_page(pmdp);
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pgtable_pmd_page_dtor(page);
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tlb_remove_table(tlb, page);
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}
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#endif
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#if CONFIG_PGTABLE_LEVELS > 3
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static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
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unsigned long addr)
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{
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tlb_remove_table(tlb, virt_to_page(pudp));
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}
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#endif
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#endif
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