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abf80c276d
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com> |
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.. | ||
bootp | ||
compressed | ||
dts | ||
.gitignore | ||
install.sh | ||
Makefile |