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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b274776c54
A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUSUyKmCrR//JCVInAQIN8RAAnb/uPytmlMjn5yCksF4Mvb/FVbn/TVwz KRIGpCHOzyKK1q7pM8NRUVWfjW2SZqbXJFqx6zBGKSlDPvFTOhsLyyupU+Tnyu5W IX4eIUBwb+a6H7XDHw0X2YI8uHzi5RNLhne0A1QyDKcnuHs1LDAttXnJHaK4Ap6Y NN2YFt3l3ld7DXWXJtMsw5v8lC10aeIFGTvXefaPDAdeMLivmI57qEUMDXknNr7W Odz/Rc0/cw3BNBVl/zNHA0jw7FOjKAymCYYNUa4xDCJEr+JnIRTqizd0N/YIIC7x aA2xjJ3oKUFyF51yiJE6nFuTyJznhwtehc+uiMOSIkjrPLym52LEHmd7G5Yqlmjz oiei09qBb870q3lGxwfht9iaeIwYgQFYGfD0yW5QWArCO5pxhtCPLPH7YZNZtcQd ZJRSGGqT/ljBz3bm0K9OLESeeTTN7+Nxvtpiz/CD+Piegz0gWJzDYJRTzkJ3UWpA WTVhVQdWUeX2JrNkgM7Z3Tu8iXOe+LIEs7kVXGJZSREmIIZiRvR36UrODZtAkp9I 7YQ+srX/uaR832pgK0RrHK0zY0psU6MmIvhYxJZFbx7keiPA9eH6drb0x7tGqcUD FzEUzvcZvyqppndfBi+R60H/YKAhJDEXdwxzo6dyCpPQaW1T9GnzIqXuE1zin+Aw X7Y8YywMbHI= =DvgJ -----END PGP SIGNATURE----- Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Arnd Bergmann: "A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code." * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits) ARM: mvebu: correct gated clock documentation ARM: kirkwood: add missing include for nsa310 ARM: exynos: move exynos4210-combiner to drivers/irqchip mfd: db8500-prcmu: update resource passing drivers/db8500-cpufreq: delete dangling include ARM: at91: remove NEOCORE 926 board sunxi: Cleanup the reset code and add meaningful registers defines ARM: S3C24XX: header mach/regs-mem.h local ARM: S3C24XX: header mach/regs-power.h local ARM: S3C24XX: header mach/regs-s3c2412-mem.h local ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/ ARM: S3C24XX: transform s3c2443 subirqs into new structure ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs ARM: S3C24XX: move s3c2443 irq code to irq.c ARM: S3C24XX: transform s3c2416 irqs into new structure ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs ARM: S3C24XX: move s3c2416 irq init to common irq code ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property ARM: S3C24XX: Move irq syscore-ops to irq-pm clocksource: always define CLOCKSOURCE_OF_DECLARE ...
378 lines
8.6 KiB
C
378 lines
8.6 KiB
C
/* linux/arch/arm/plat-s3c64xx/pm.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX CPU PM support.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/pm_domain.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/wakeup-mask.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include "regs-gpio-memport.h"
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#include "regs-modem.h"
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#include "regs-sys.h"
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#include "regs-syscon-power.h"
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struct s3c64xx_pm_domain {
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char *const name;
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u32 ena;
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u32 pwr_stat;
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struct generic_pm_domain pd;
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};
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static int s3c64xx_pd_off(struct generic_pm_domain *domain)
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{
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struct s3c64xx_pm_domain *pd;
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u32 val;
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pd = container_of(domain, struct s3c64xx_pm_domain, pd);
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val = __raw_readl(S3C64XX_NORMAL_CFG);
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val &= ~(pd->ena);
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__raw_writel(val, S3C64XX_NORMAL_CFG);
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return 0;
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}
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static int s3c64xx_pd_on(struct generic_pm_domain *domain)
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{
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struct s3c64xx_pm_domain *pd;
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u32 val;
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long retry = 1000000L;
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pd = container_of(domain, struct s3c64xx_pm_domain, pd);
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val = __raw_readl(S3C64XX_NORMAL_CFG);
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val |= pd->ena;
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__raw_writel(val, S3C64XX_NORMAL_CFG);
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/* Not all domains provide power status readback */
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if (pd->pwr_stat) {
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do {
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cpu_relax();
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if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
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break;
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} while (retry--);
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if (!retry) {
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pr_err("Failed to start domain %s\n", pd->name);
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return -EBUSY;
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}
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}
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return 0;
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}
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static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
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.name = "IROM",
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.ena = S3C64XX_NORMALCFG_IROM_ON,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
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.name = "ETM",
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.ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_s = {
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.name = "S",
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.ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_S,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_f = {
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.name = "F",
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.ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_F,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_p = {
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.name = "P",
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.ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_P,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_i = {
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.name = "I",
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.ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_I,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_g = {
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.name = "G",
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.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain s3c64xx_pm_v = {
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.name = "V",
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.ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
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.pwr_stat = S3C64XX_BLKPWRSTAT_V,
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.pd = {
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.power_off = s3c64xx_pd_off,
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.power_on = s3c64xx_pd_on,
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},
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};
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static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
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&s3c64xx_pm_irom,
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};
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static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
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&s3c64xx_pm_etm,
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&s3c64xx_pm_g,
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&s3c64xx_pm_v,
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&s3c64xx_pm_i,
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&s3c64xx_pm_p,
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&s3c64xx_pm_s,
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&s3c64xx_pm_f,
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};
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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void s3c_pm_debug_smdkled(u32 set, u32 clear)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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for (i = 0; i < 4; i++) {
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if (clear & (1 << i))
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gpio_set_value(S3C64XX_GPN(12 + i), 0);
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if (set & (1 << i))
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gpio_set_value(S3C64XX_GPN(12 + i), 1);
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}
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local_irq_restore(flags);
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}
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#endif
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static struct sleep_save core_save[] = {
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SAVE_ITEM(S3C_APLL_LOCK),
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SAVE_ITEM(S3C_MPLL_LOCK),
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SAVE_ITEM(S3C_EPLL_LOCK),
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SAVE_ITEM(S3C_CLK_SRC),
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SAVE_ITEM(S3C_CLK_DIV0),
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SAVE_ITEM(S3C_CLK_DIV1),
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SAVE_ITEM(S3C_CLK_DIV2),
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SAVE_ITEM(S3C_CLK_OUT),
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SAVE_ITEM(S3C_HCLK_GATE),
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SAVE_ITEM(S3C_PCLK_GATE),
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SAVE_ITEM(S3C_SCLK_GATE),
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SAVE_ITEM(S3C_MEM0_GATE),
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SAVE_ITEM(S3C_EPLL_CON1),
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SAVE_ITEM(S3C_EPLL_CON0),
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SAVE_ITEM(S3C64XX_MEM0DRVCON),
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SAVE_ITEM(S3C64XX_MEM1DRVCON),
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#ifndef CONFIG_CPU_FREQ
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SAVE_ITEM(S3C_APLL_CON),
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SAVE_ITEM(S3C_MPLL_CON),
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#endif
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};
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static struct sleep_save misc_save[] = {
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SAVE_ITEM(S3C64XX_AHB_CON0),
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SAVE_ITEM(S3C64XX_AHB_CON1),
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SAVE_ITEM(S3C64XX_AHB_CON2),
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SAVE_ITEM(S3C64XX_SPCON),
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SAVE_ITEM(S3C64XX_MEM0CONSTOP),
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SAVE_ITEM(S3C64XX_MEM1CONSTOP),
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SAVE_ITEM(S3C64XX_MEM0CONSLP0),
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SAVE_ITEM(S3C64XX_MEM0CONSLP1),
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SAVE_ITEM(S3C64XX_MEM1CONSLP),
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SAVE_ITEM(S3C64XX_SDMA_SEL),
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SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
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SAVE_ITEM(S3C64XX_NORMAL_CFG),
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};
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void s3c_pm_configure_extint(void)
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{
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__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
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}
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void s3c_pm_restore_core(void)
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{
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__raw_writel(0, S3C64XX_EINT_MASK);
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s3c_pm_debug_smdkled(1 << 2, 0);
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s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
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s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
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}
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void s3c_pm_save_core(void)
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{
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s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
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s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
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}
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/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
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* put the per-cpu code in here until any new cpu comes along and changes
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* this.
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*/
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static int s3c64xx_cpu_suspend(unsigned long arg)
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{
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unsigned long tmp;
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/* set our standby method to sleep */
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tmp = __raw_readl(S3C64XX_PWR_CFG);
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tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
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tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
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__raw_writel(tmp, S3C64XX_PWR_CFG);
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/* clear any old wakeup */
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__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
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S3C64XX_WAKEUP_STAT);
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/* set the LED state to 0110 over sleep */
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s3c_pm_debug_smdkled(3 << 1, 0xf);
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/* issue the standby signal into the pm unit. Note, we
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* issue a write-buffer drain just in case */
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tmp = 0;
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asm("b 1f\n\t"
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".align 5\n\t"
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"1:\n\t"
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"mcr p15, 0, %0, c7, c10, 5\n\t"
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"mcr p15, 0, %0, c7, c10, 4\n\t"
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"mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
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/* we should never get past here */
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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/* mapping of interrupts to parts of the wakeup mask */
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static struct samsung_wakeup_mask wake_irqs[] = {
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{ .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
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{ .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
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{ .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
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{ .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
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{ .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
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{ .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
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{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
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};
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static void s3c64xx_pm_prepare(void)
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{
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samsung_sync_wakemask(S3C64XX_PWR_CFG,
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wake_irqs, ARRAY_SIZE(wake_irqs));
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/* store address of resume. */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
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/* ensure previous wakeup state is cleared before sleeping */
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__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
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}
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int __init s3c64xx_pm_init(void)
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{
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int i;
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s3c_pm_init();
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for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
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pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
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&pm_domain_always_on_gov, false);
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for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
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pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
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#ifdef CONFIG_S3C_DEV_FB
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if (dev_get_platdata(&s3c_device_fb.dev))
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pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
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#endif
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return 0;
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}
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static __init int s3c64xx_pm_initcall(void)
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{
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pm_cpu_prep = s3c64xx_pm_prepare;
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pm_cpu_sleep = s3c64xx_cpu_suspend;
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pm_uart_udivslot = 1;
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
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gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
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gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
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gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
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gpio_direction_output(S3C64XX_GPN(12), 0);
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gpio_direction_output(S3C64XX_GPN(13), 0);
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gpio_direction_output(S3C64XX_GPN(14), 0);
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gpio_direction_output(S3C64XX_GPN(15), 0);
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#endif
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return 0;
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}
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arch_initcall(s3c64xx_pm_initcall);
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int __init s3c64xx_pm_late_initcall(void)
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{
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pm_genpd_poweroff_unused();
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return 0;
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}
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