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72fd9bc8f5
Add pinctrl binding doc update for imx6sll. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
41 lines
1.6 KiB
Plaintext
41 lines
1.6 KiB
Plaintext
* Freescale i.MX6 SLL IOMUX Controller
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
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and usage.
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Required properties:
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- compatible: "fsl,imx6sll-iomuxc"
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- fsl,pins: each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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input_val> are specified using a PIN_FUNC_ID macro, which can be found in
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imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
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the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
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Reference Manual for detailed CONFIG settings.
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CONFIG bits definition:
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PAD_CTL_LVE (1 << 22)
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PAD_CTL_HYS (1 << 16)
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PAD_CTL_PUS_100K_DOWN (0 << 14)
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PAD_CTL_PUS_47K_UP (1 << 14)
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PAD_CTL_PUS_100K_UP (2 << 14)
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PAD_CTL_PUS_22K_UP (3 << 14)
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PAD_CTL_PUE (1 << 13)
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PAD_CTL_PKE (1 << 12)
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PAD_CTL_ODE (1 << 11)
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PAD_CTL_SPEED_LOW (0 << 6)
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PAD_CTL_SPEED_MED (1 << 6)
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PAD_CTL_SPEED_HIGH (3 << 6)
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PAD_CTL_DSE_DISABLE (0 << 3)
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PAD_CTL_DSE_260ohm (1 << 3)
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PAD_CTL_DSE_130ohm (2 << 3)
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PAD_CTL_DSE_87ohm (3 << 3)
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PAD_CTL_DSE_65ohm (4 << 3)
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PAD_CTL_DSE_52ohm (5 << 3)
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PAD_CTL_DSE_43ohm (6 << 3)
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PAD_CTL_DSE_37ohm (7 << 3)
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PAD_CTL_SRE_FAST (1 << 0)
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PAD_CTL_SRE_SLOW (0 << 0)
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Refer to imx6sll-pinfunc.h in device tree source folder for all available
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imx6sll PIN_FUNC_ID.
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