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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4a33bea003
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
33 lines
745 B
Makefile
33 lines
745 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the phy drivers.
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#
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obj-$(CONFIG_GENERIC_PHY) += phy-core.o
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obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
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obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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obj-y += allwinner/ \
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amlogic/ \
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broadcom/ \
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cadence/ \
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freescale/ \
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hisilicon/ \
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intel/ \
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lantiq/ \
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marvell/ \
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mediatek/ \
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motorola/ \
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mscc/ \
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qualcomm/ \
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ralink/ \
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renesas/ \
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rockchip/ \
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samsung/ \
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socionext/ \
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st/ \
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tegra/ \
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ti/ \
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xilinx/
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