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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4726214c54
When multiple VFs try to enter exclusive mode at the same time, the looping mechansim doesn't help to ensure each can get it because it only loops active VFs, then the last one has to wait for a long interval. Signed-off-by: Pixel Ding <Pixel.Ding@amd.com> Reviewed-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
56 lines
1.9 KiB
C
56 lines
1.9 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __MXGPU_VI_H__
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#define __MXGPU_VI_H__
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#define VI_MAILBOX_TIMEDOUT 5000
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#define VI_MAILBOX_RESET_TIME 12
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/* VI mailbox messages request */
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enum idh_request {
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IDH_REQ_GPU_INIT_ACCESS = 1,
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IDH_REL_GPU_INIT_ACCESS,
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IDH_REQ_GPU_FINI_ACCESS,
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IDH_REL_GPU_FINI_ACCESS,
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IDH_REQ_GPU_RESET_ACCESS
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};
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/* VI mailbox messages data */
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enum idh_event {
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IDH_CLR_MSG_BUF = 0,
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IDH_READY_TO_ACCESS_GPU,
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IDH_FLR_NOTIFICATION,
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IDH_FLR_NOTIFICATION_CMPL,
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IDH_EVENT_MAX
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};
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extern const struct amdgpu_virt_ops xgpu_vi_virt_ops;
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void xgpu_vi_init_golden_registers(struct amdgpu_device *adev);
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void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev);
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int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev);
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int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev);
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void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev);
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#endif
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