Sung Lee aad927b5a8 drm/amd/display: Use dcfclk to populate watermark ranges ... [WHY & HOW] Previously drain clk was unconstrained and fill clk was constrained on fclk. We want to change it to fill clk unconstrained and drain clock constrained to dcfclk. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-11 12:15:02 -05:00
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acp
amdgpu	drm fixes for 5.6-rc1	2020-02-07 12:46:08 -08:00
amdkfd	drm/amdkfd: Fix a bug in SDMA RLC queue counting under HWS mode	2020-02-04 10:32:41 -05:00
display	drm/amd/display: Use dcfclk to populate watermark ranges	2020-02-11 12:15:02 -05:00
include	drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus	2020-01-30 17:15:27 -05:00
powerplay	drm/amdgpu: update default voltage for boot od table for navi1x	2020-02-04 23:30:38 -05:00