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aac5e972d4
Add audio driver node for mt2701 Signed-off-by: Garlic Tseng <garlic.tseng@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
606 lines
16 KiB
Plaintext
606 lines
16 KiB
Plaintext
/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Erin.Lo <erin.lo@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include "skeleton64.dtsi"
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#include "mt2701-pinfunc.h"
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/ {
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compatible = "mediatek,mt2701";
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interrupt-parent = <&cirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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rtc32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&thermal 0>;
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sustainable-power = <1000>;
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trips {
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threshold: trip-point@0 {
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temperature = <68000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point@1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit@0 {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt2701-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt2701-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt2701-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt2701-scpsys", "syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt2701-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt2701-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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pio: pinctrl@1000b000 {
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compatible = "mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt2701-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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cirq: interrupt-controller@10204000 {
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compatible = "mediatek,mt2701-cirq",
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"mediatek,mtk-cirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&sysirq>;
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reg = <0 0x10204000 0 0x400>;
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mediatek,ext-irq-range = <32 200>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2701-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x2000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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auxadc: adc@11001000 {
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compatible = "mediatek,mt2701-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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clock-names = "main";
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#io-channel-cells = <1>;
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt2701-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11007000 0 0x70>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt2701-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt2701-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <0>;
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compatible = "mediatek,mt2701-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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nandc: nfi@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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status = "disabled";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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status = "disabled";
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};
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nor_flash: spi@11014000 {
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compatible = "mediatek,mt2701-nor",
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"mediatek,mt8173-nor";
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reg = <0 0x11014000 0 0xe0>;
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clocks = <&pericfg CLK_PERI_FLASH>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@11016000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11016000 0 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI1_SEL>,
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<&pericfg CLK_PERI_SPI1>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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spi2: spi@11017000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11017000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI2_SEL>,
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<&pericfg CLK_PERI_SPI2>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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afe: audio-controller@11220000 {
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compatible = "mediatek,mt2701-audio";
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reg = <0 0x11220000 0 0x2000>,
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<0 0x112a0000 0 0x20000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
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<&topckgen CLK_TOP_APLL_SEL>,
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<&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>,
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<&topckgen CLK_TOP_HADDS2PLL_98M>,
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<&topckgen CLK_TOP_HADDS2PLL_294M>,
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<&topckgen CLK_TOP_AUDPLL>,
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<&topckgen CLK_TOP_AUDPLL_D4>,
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<&topckgen CLK_TOP_AUDPLL_D8>,
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<&topckgen CLK_TOP_AUDPLL_D16>,
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<&topckgen CLK_TOP_AUDPLL_D24>,
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<&topckgen CLK_TOP_AUDINTBUS_SEL>,
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<&clk26m>,
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<&topckgen CLK_TOP_SYSPLL1_D4>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
|
|
<&topckgen CLK_TOP_ASM_M_SEL>,
|
|
<&topckgen CLK_TOP_ASM_H_SEL>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D4>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D2>,
|
|
<&topckgen CLK_TOP_SYSPLL_D5>;
|
|
|
|
clock-names = "infra_sys_audio_clk",
|
|
"top_audio_mux1_sel",
|
|
"top_audio_mux2_sel",
|
|
"top_audio_mux1_div",
|
|
"top_audio_mux2_div",
|
|
"top_audio_48k_timing",
|
|
"top_audio_44k_timing",
|
|
"top_audpll_mux_sel",
|
|
"top_apll_sel",
|
|
"top_aud1_pll_98M",
|
|
"top_aud2_pll_90M",
|
|
"top_hadds2_pll_98M",
|
|
"top_hadds2_pll_294M",
|
|
"top_audpll",
|
|
"top_audpll_d4",
|
|
"top_audpll_d8",
|
|
"top_audpll_d16",
|
|
"top_audpll_d24",
|
|
"top_audintbus_sel",
|
|
"clk_26m",
|
|
"top_syspll1_d4",
|
|
"top_aud_k1_src_sel",
|
|
"top_aud_k2_src_sel",
|
|
"top_aud_k3_src_sel",
|
|
"top_aud_k4_src_sel",
|
|
"top_aud_k5_src_sel",
|
|
"top_aud_k6_src_sel",
|
|
"top_aud_k1_src_div",
|
|
"top_aud_k2_src_div",
|
|
"top_aud_k3_src_div",
|
|
"top_aud_k4_src_div",
|
|
"top_aud_k5_src_div",
|
|
"top_aud_k6_src_div",
|
|
"top_aud_i2s1_mclk",
|
|
"top_aud_i2s2_mclk",
|
|
"top_aud_i2s3_mclk",
|
|
"top_aud_i2s4_mclk",
|
|
"top_aud_i2s5_mclk",
|
|
"top_aud_i2s6_mclk",
|
|
"top_asm_m_sel",
|
|
"top_asm_h_sel",
|
|
"top_univpll2_d4",
|
|
"top_univpll2_d2",
|
|
"top_syspll_d5";
|
|
};
|
|
|
|
mmsys: syscon@14000000 {
|
|
compatible = "mediatek,mt2701-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb0: larb@14010000 {
|
|
compatible = "mediatek,mt2701-smi-larb";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&mmsys CLK_MM_SMI_LARB0>,
|
|
<&mmsys CLK_MM_SMI_LARB0>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
|
|
};
|
|
|
|
imgsys: syscon@15000000 {
|
|
compatible = "mediatek,mt2701-imgsys", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb2: larb@15001000 {
|
|
compatible = "mediatek,mt2701-smi-larb";
|
|
reg = <0 0x15001000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&imgsys CLK_IMG_SMI_COMM>,
|
|
<&imgsys CLK_IMG_SMI_COMM>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
|
};
|
|
|
|
jpegdec: jpegdec@15004000 {
|
|
compatible = "mediatek,mt2701-jpgdec";
|
|
reg = <0 0x15004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
|
|
<&imgsys CLK_IMG_JPGDEC>;
|
|
clock-names = "jpgdec-smi",
|
|
"jpgdec";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
|
mediatek,larb = <&larb2>;
|
|
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
|
|
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
|
|
};
|
|
|
|
vdecsys: syscon@16000000 {
|
|
compatible = "mediatek,mt2701-vdecsys", "syscon";
|
|
reg = <0 0x16000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb1: larb@16010000 {
|
|
compatible = "mediatek,mt2701-smi-larb";
|
|
reg = <0 0x16010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
clocks = <&vdecsys CLK_VDEC_CKGEN>,
|
|
<&vdecsys CLK_VDEC_LARB>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
|
|
};
|
|
|
|
hifsys: syscon@1a000000 {
|
|
compatible = "mediatek,mt2701-hifsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
ethsys: syscon@1b000000 {
|
|
compatible = "mediatek,mt2701-ethsys", "syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
bdpsys: syscon@1c000000 {
|
|
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
|
reg = <0 0x1c000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|