mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
55 lines
1.2 KiB
Plaintext
55 lines
1.2 KiB
Plaintext
Driver for PXA25x LCD controller
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The driver supports the following options, either via
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options=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in.
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For example:
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modprobe pxafb options=mode:640x480-8,passive
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or on the kernel command line
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video=pxafb:mode:640x480-8,passive
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mode:XRESxYRES[-BPP]
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XRES == LCCR1_PPL + 1
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YRES == LLCR2_LPP + 1
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The resolution of the display in pixels
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BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16.
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pixclock:PIXCLOCK
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Pixel clock in picoseconds
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left:LEFT == LCCR1_BLW + 1
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right:RIGHT == LCCR1_ELW + 1
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hsynclen:HSYNC == LCCR1_HSW + 1
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upper:UPPER == LCCR2_BFW
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lower:LOWER == LCCR2_EFR
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vsynclen:VSYNC == LCCR2_VSW + 1
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Display margins and sync times
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color | mono => LCCR0_CMS
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umm...
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active | passive => LCCR0_PAS
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Active (TFT) or Passive (STN) display
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single | dual => LCCR0_SDS
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Single or dual panel passive display
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4pix | 8pix => LCCR0_DPD
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4 or 8 pixel monochrome single panel data
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hsync:HSYNC
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vsync:VSYNC
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Horizontal and vertical sync. 0 => active low, 1 => active
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high.
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dpc:DPC
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Double pixel clock. 1=>true, 0=>false
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outputen:POLARITY
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Output Enable Polarity. 0 => active low, 1 => active high
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pixclockpol:POLARITY
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pixel clock polarity
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0 => falling edge, 1 => rising edge
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