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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b0f7b8bc57
Add support for the AMCC PowerPC 440SPe SoC, including PCI Express in root port mode. Signed-off-by: Roland Dreier <rolandd@cisco.com> Cc: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/*
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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* Roland Dreier <rolandd@cisco.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H
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#define __PPC_SYSLIB_PPC440SPE_PCIE_H
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#define DCRN_SDR0_CFGADDR 0x00e
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#define DCRN_SDR0_CFGDATA 0x00f
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#define DCRN_PCIE0_BASE 0x100
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#define DCRN_PCIE1_BASE 0x120
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#define DCRN_PCIE2_BASE 0x140
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#define PCIE0 DCRN_PCIE0_BASE
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#define PCIE1 DCRN_PCIE1_BASE
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#define PCIE2 DCRN_PCIE2_BASE
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#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
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#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
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#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
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#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
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#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
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#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
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#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
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#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
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#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
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#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
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#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
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#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
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#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
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#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
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/*
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* System DCRs (SDRs)
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*/
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#define PESDR0_PLLLCT1 0x03a0
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#define PESDR0_PLLLCT2 0x03a1
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#define PESDR0_PLLLCT3 0x03a2
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#define PESDR0_UTLSET1 0x0300
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#define PESDR0_UTLSET2 0x0301
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#define PESDR0_DLPSET 0x0302
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#define PESDR0_LOOP 0x0303
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#define PESDR0_RCSSET 0x0304
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#define PESDR0_RCSSTS 0x0305
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#define PESDR0_HSSL0SET1 0x0306
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#define PESDR0_HSSL0SET2 0x0307
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#define PESDR0_HSSL0STS 0x0308
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#define PESDR0_HSSL1SET1 0x0309
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#define PESDR0_HSSL1SET2 0x030a
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#define PESDR0_HSSL1STS 0x030b
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#define PESDR0_HSSL2SET1 0x030c
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#define PESDR0_HSSL2SET2 0x030d
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#define PESDR0_HSSL2STS 0x030e
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#define PESDR0_HSSL3SET1 0x030f
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#define PESDR0_HSSL3SET2 0x0310
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#define PESDR0_HSSL3STS 0x0311
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#define PESDR0_HSSL4SET1 0x0312
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#define PESDR0_HSSL4SET2 0x0313
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#define PESDR0_HSSL4STS 0x0314
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#define PESDR0_HSSL5SET1 0x0315
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#define PESDR0_HSSL5SET2 0x0316
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#define PESDR0_HSSL5STS 0x0317
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#define PESDR0_HSSL6SET1 0x0318
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#define PESDR0_HSSL6SET2 0x0319
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#define PESDR0_HSSL6STS 0x031a
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#define PESDR0_HSSL7SET1 0x031b
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#define PESDR0_HSSL7SET2 0x031c
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#define PESDR0_HSSL7STS 0x031d
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#define PESDR0_HSSCTLSET 0x031e
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#define PESDR0_LANE_ABCD 0x031f
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#define PESDR0_LANE_EFGH 0x0320
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#define PESDR1_UTLSET1 0x0340
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#define PESDR1_UTLSET2 0x0341
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#define PESDR1_DLPSET 0x0342
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#define PESDR1_LOOP 0x0343
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#define PESDR1_RCSSET 0x0344
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#define PESDR1_RCSSTS 0x0345
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#define PESDR1_HSSL0SET1 0x0346
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#define PESDR1_HSSL0SET2 0x0347
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#define PESDR1_HSSL0STS 0x0348
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#define PESDR1_HSSL1SET1 0x0349
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#define PESDR1_HSSL1SET2 0x034a
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#define PESDR1_HSSL1STS 0x034b
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#define PESDR1_HSSL2SET1 0x034c
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#define PESDR1_HSSL2SET2 0x034d
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#define PESDR1_HSSL2STS 0x034e
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#define PESDR1_HSSL3SET1 0x034f
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#define PESDR1_HSSL3SET2 0x0350
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#define PESDR1_HSSL3STS 0x0351
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#define PESDR1_HSSCTLSET 0x0352
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#define PESDR1_LANE_ABCD 0x0353
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#define PESDR2_UTLSET1 0x0370
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#define PESDR2_UTLSET2 0x0371
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#define PESDR2_DLPSET 0x0372
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#define PESDR2_LOOP 0x0373
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#define PESDR2_RCSSET 0x0374
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#define PESDR2_RCSSTS 0x0375
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#define PESDR2_HSSL0SET1 0x0376
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#define PESDR2_HSSL0SET2 0x0377
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#define PESDR2_HSSL0STS 0x0378
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#define PESDR2_HSSL1SET1 0x0379
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#define PESDR2_HSSL1SET2 0x037a
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#define PESDR2_HSSL1STS 0x037b
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#define PESDR2_HSSL2SET1 0x037c
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#define PESDR2_HSSL2SET2 0x037d
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#define PESDR2_HSSL2STS 0x037e
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#define PESDR2_HSSL3SET1 0x037f
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#define PESDR2_HSSL3SET2 0x0380
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#define PESDR2_HSSL3STS 0x0381
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#define PESDR2_HSSCTLSET 0x0382
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#define PESDR2_LANE_ABCD 0x0383
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/*
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* UTL register offsets
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*/
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#define PEUTL_PBBSZ 0x20
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#define PEUTL_OPDBSZ 0x68
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#define PEUTL_IPHBSZ 0x70
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#define PEUTL_IPDBSZ 0x78
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#define PEUTL_OUTTR 0x90
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#define PEUTL_INTR 0x98
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#define PEUTL_PCTL 0xa0
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#define PEUTL_RCIRQEN 0xb8
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/*
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* Config space register offsets
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*/
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#define PECFG_BAR0LMPA 0x210
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#define PECFG_BAR0HMPA 0x214
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#define PECFG_PIMEN 0x33c
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#define PECFG_PIM0LAL 0x340
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#define PECFG_PIM0LAH 0x344
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#define PECFG_POM0LAL 0x380
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#define PECFG_POM0LAH 0x384
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int ppc440spe_init_pcie(void);
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int ppc440spe_init_pcie_rootport(int port);
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void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
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#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */
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