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70db8b79e5
Explicit clock enabling is required on 6sll and 6ull so mention that standard clock bindings are used. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
19 lines
617 B
Plaintext
19 lines
617 B
Plaintext
Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28 .
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Required properties:
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- compatible : Should be "fsl,<soc>-dcp"
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- reg : Should contain MXS DCP registers location and length
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- interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
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must be supplied, optionally Secure IRQ can be present, but
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is currently not implemented and not used.
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- clocks : Clock reference (only required on some SOCs: 6ull and 6sll).
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- clock-names : Must be "dcp".
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Example:
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dcp@80028000 {
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compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
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reg = <0x80028000 0x2000>;
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interrupts = <52 53>;
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};
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