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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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02e32e36f4
paravirtualize minstate.h which are hand written assembly code. They include sensitive or performance critical privileged instructions. So that they are appropriate for paravirtualization. Cc: Keith Owens <kaos@ocs.com.au> Cc: Akio Takebe <takebe_akio@jp.fujitsu.com> Signed-off-by: Yaozu (Eddie) Dong <eddie.dong@intel.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
251 lines
8.0 KiB
C
251 lines
8.0 KiB
C
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#include <asm/cache.h>
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#include "entry.h"
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#include "paravirt_inst.h"
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#ifdef CONFIG_VIRT_CPU_ACCOUNTING
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/* read ar.itc in advance, and use it before leaving bank 0 */
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#define ACCOUNT_GET_STAMP \
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(pUStk) mov.m r20=ar.itc;
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#define ACCOUNT_SYS_ENTER \
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(pUStk) br.call.spnt rp=account_sys_enter \
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;;
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#else
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#define ACCOUNT_GET_STAMP
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#define ACCOUNT_SYS_ENTER
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#endif
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.section ".data.patch.rse", "a"
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.previous
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/*
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* DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
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* the minimum state necessary that allows us to turn psr.ic back
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* on.
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*
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* Assumed state upon entry:
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* psr.ic: off
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* r31: contains saved predicates (pr)
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*
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* Upon exit, the state is as follows:
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* psr.ic: off
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* r2 = points to &pt_regs.r16
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* r8 = contents of ar.ccv
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* r9 = contents of ar.csd
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* r10 = contents of ar.ssd
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* r11 = FPSR_DEFAULT
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* r12 = kernel sp (kernel virtual address)
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* r13 = points to current task_struct (kernel virtual address)
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* p15 = TRUE if psr.i is set in cr.ipsr
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* predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
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* preserved
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*
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* Note that psr.ic is NOT turned on by this macro. This is so that
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* we can pass interruption state as arguments to a handler.
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*/
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#define IA64_NATIVE_DO_SAVE_MIN(__COVER,SAVE_IFS,EXTRA,WORKAROUND) \
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mov r16=IA64_KR(CURRENT); /* M */ \
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mov r27=ar.rsc; /* M */ \
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mov r20=r1; /* A */ \
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mov r25=ar.unat; /* M */ \
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MOV_FROM_IPSR(p0,r29); /* M */ \
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mov r26=ar.pfs; /* I */ \
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MOV_FROM_IIP(r28); /* M */ \
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mov r21=ar.fpsr; /* M */ \
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__COVER; /* B;; (or nothing) */ \
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;; \
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adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
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;; \
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ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
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st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
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adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
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/* switch from user to kernel RBS: */ \
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;; \
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invala; /* M */ \
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SAVE_IFS; \
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cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \
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;; \
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(pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
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;; \
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(pUStk) mov.m r24=ar.rnat; \
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(pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
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(pKStk) mov r1=sp; /* get sp */ \
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;; \
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(pUStk) lfetch.fault.excl.nt1 [r22]; \
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(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
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(pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
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;; \
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(pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
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(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
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;; \
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(pUStk) mov r18=ar.bsp; \
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(pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
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adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
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adds r16=PT(CR_IPSR),r1; \
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;; \
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lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
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st8 [r16]=r29; /* save cr.ipsr */ \
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;; \
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lfetch.fault.excl.nt1 [r17]; \
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tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \
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mov r29=b0 \
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;; \
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WORKAROUND; \
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adds r16=PT(R8),r1; /* initialize first base pointer */ \
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adds r17=PT(R9),r1; /* initialize second base pointer */ \
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(pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \
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;; \
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.mem.offset 0,0; st8.spill [r16]=r8,16; \
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.mem.offset 8,0; st8.spill [r17]=r9,16; \
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;; \
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.mem.offset 0,0; st8.spill [r16]=r10,24; \
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.mem.offset 8,0; st8.spill [r17]=r11,24; \
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;; \
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st8 [r16]=r28,16; /* save cr.iip */ \
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st8 [r17]=r30,16; /* save cr.ifs */ \
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(pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
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mov r8=ar.ccv; \
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mov r9=ar.csd; \
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mov r10=ar.ssd; \
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movl r11=FPSR_DEFAULT; /* L-unit */ \
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;; \
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st8 [r16]=r25,16; /* save ar.unat */ \
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st8 [r17]=r26,16; /* save ar.pfs */ \
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shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
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;; \
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st8 [r16]=r27,16; /* save ar.rsc */ \
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(pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \
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(pKStk) adds r17=16,r17; /* skip over ar_rnat field */ \
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;; /* avoid RAW on r16 & r17 */ \
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(pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \
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st8 [r17]=r31,16; /* save predicates */ \
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(pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \
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;; \
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st8 [r16]=r29,16; /* save b0 */ \
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st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
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cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \
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;; \
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.mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
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.mem.offset 8,0; st8.spill [r17]=r12,16; \
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adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
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;; \
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.mem.offset 0,0; st8.spill [r16]=r13,16; \
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.mem.offset 8,0; st8.spill [r17]=r21,16; /* save ar.fpsr */ \
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mov r13=IA64_KR(CURRENT); /* establish `current' */ \
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;; \
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.mem.offset 0,0; st8.spill [r16]=r15,16; \
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.mem.offset 8,0; st8.spill [r17]=r14,16; \
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;; \
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.mem.offset 0,0; st8.spill [r16]=r2,16; \
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.mem.offset 8,0; st8.spill [r17]=r3,16; \
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ACCOUNT_GET_STAMP \
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adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
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;; \
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EXTRA; \
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movl r1=__gp; /* establish kernel global pointer */ \
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;; \
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ACCOUNT_SYS_ENTER \
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bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
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;;
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/*
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* SAVE_REST saves the remainder of pt_regs (with psr.ic on).
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*
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* Assumed state upon entry:
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* psr.ic: on
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* r2: points to &pt_regs.r16
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* r3: points to &pt_regs.r17
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* r8: contents of ar.ccv
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* r9: contents of ar.csd
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* r10: contents of ar.ssd
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* r11: FPSR_DEFAULT
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*
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* Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
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*/
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#define SAVE_REST \
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.mem.offset 0,0; st8.spill [r2]=r16,16; \
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.mem.offset 8,0; st8.spill [r3]=r17,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r18,16; \
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.mem.offset 8,0; st8.spill [r3]=r19,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r20,16; \
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.mem.offset 8,0; st8.spill [r3]=r21,16; \
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mov r18=b6; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r22,16; \
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.mem.offset 8,0; st8.spill [r3]=r23,16; \
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mov r19=b7; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r24,16; \
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.mem.offset 8,0; st8.spill [r3]=r25,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r26,16; \
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.mem.offset 8,0; st8.spill [r3]=r27,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r28,16; \
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.mem.offset 8,0; st8.spill [r3]=r29,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2]=r30,16; \
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.mem.offset 8,0; st8.spill [r3]=r31,32; \
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;; \
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mov ar.fpsr=r11; /* M-unit */ \
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st8 [r2]=r8,8; /* ar.ccv */ \
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adds r24=PT(B6)-PT(F7),r3; \
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;; \
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stf.spill [r2]=f6,32; \
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stf.spill [r3]=f7,32; \
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;; \
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stf.spill [r2]=f8,32; \
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stf.spill [r3]=f9,32; \
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;; \
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stf.spill [r2]=f10; \
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stf.spill [r3]=f11; \
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adds r25=PT(B7)-PT(F11),r3; \
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;; \
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st8 [r24]=r18,16; /* b6 */ \
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st8 [r25]=r19,16; /* b7 */ \
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;; \
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st8 [r24]=r9; /* ar.csd */ \
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st8 [r25]=r10; /* ar.ssd */ \
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;;
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#define RSE_WORKAROUND \
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(pUStk) extr.u r17=r18,3,6; \
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(pUStk) sub r16=r18,r22; \
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[1:](pKStk) br.cond.sptk.many 1f; \
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.xdata4 ".data.patch.rse",1b-. \
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;; \
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cmp.ge p6,p7 = 33,r17; \
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;; \
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(p6) mov r17=0x310; \
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(p7) mov r17=0x308; \
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;; \
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cmp.leu p1,p0=r16,r17; \
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(p1) br.cond.sptk.many 1f; \
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dep.z r17=r26,0,62; \
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movl r16=2f; \
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;; \
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mov ar.pfs=r17; \
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dep r27=r0,r27,16,14; \
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mov b0=r16; \
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;; \
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br.ret.sptk b0; \
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;; \
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2: \
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mov ar.rsc=r0 \
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;; \
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flushrs; \
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;; \
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mov ar.bspstore=r22 \
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;; \
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mov r18=ar.bsp; \
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;; \
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1: \
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.pred.rel "mutex", pKStk, pUStk
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#define SAVE_MIN_WITH_COVER DO_SAVE_MIN(COVER, mov r30=cr.ifs, , RSE_WORKAROUND)
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#define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(COVER, mov r30=cr.ifs, mov r15=r19, RSE_WORKAROUND)
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#define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, , )
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