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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f8a15f9766
ARCv2 optimized memcpy uses PREFETCHW instruction for prefetching the next cache line but doesn't ensure that the line is not past the end of the buffer. PRETECHW changes the line ownership and marks it dirty, which can cause data corruption if this area is used for DMA IO. Fix the issue by avoiding the PREFETCHW. This leads to performance degradation but it is OK as we'll introduce new memcpy implementation optimized for unaligned memory access using. We also cut off all PREFETCH instructions at they are quite useless here: * we call PREFETCH right before LOAD instruction call. * we copy 16 or 32 bytes of data (depending on CONFIG_ARC_HAS_LL64) in a main logical loop. so we call PREFETCH 4 times (or 2 times) for each L1 cache line (in case of 64B L1 cache Line which is default case). Obviously this is not optimal. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> |
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| .. | ||
| Makefile | ||
| memcmp.S | ||
| memcpy-700.S | ||
| memcpy-archs.S | ||
| memset-archs.S | ||
| memset.S | ||
| strchr-700.S | ||
| strcmp-archs.S | ||
| strcmp.S | ||
| strcpy-700.S | ||
| strlen.S | ||