Ilan Tayari a9956d35d1 net/mlx5: FPGA, Add SBU infrastructure ... Add interface to initialize and interact with Innova FPGA SBU connections. A client driver may use these functions to set up a high-speed DMA connection with its SBU hardware logic, and send/receive messages over this connection. A later patch in this patchset will make use of these functions for Innova IPSec offload in mlx5 Ethernet driver. Add commands to retrieve Innova FPGA SBU capabilities, and to read/write Innova FPGA configuration space registers and memory, over internal I2C. At high level, the FPGA configuration space is divided such: 0x00000000 - 0x007fffff is reserved for the SBU 0x00800000 - 0xffffffff is reserved for the Shell 0x400000000 - ... is DDR memory A later patchset will add support for accessing FPGA CrSpace and memory over a high-speed connection. This is the reason for the ACCESS_TYPE enumeration, which currently only supports I2C. Signed-off-by: Ilan Tayari <ilant@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>		2017-06-27 16:36:47 +03:00
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cmd.h
cq.h	IB/mlx5: Support 4k UAR for libmlx5	2017-01-09 20:25:09 +02:00
device.h	net/mlx5: FPGA, Add SBU infrastructure	2017-06-27 16:36:47 +03:00
doorbell.h	IB/mlx5: Use blue flame register allocator in mlx5_ib	2017-01-09 20:25:08 +02:00
driver.h	net/mlx5: FPGA, Add SBU infrastructure	2017-06-27 16:36:47 +03:00
fs.h	net/mlx5: Use underlay QPN from the root name space	2017-05-14 13:33:45 +03:00
mlx5_ifc_fpga.h	net/mlx5: FPGA, Add SBU infrastructure	2017-06-27 16:36:47 +03:00
mlx5_ifc.h	net/mlx5: FPGA, Add SBU infrastructure	2017-06-27 16:36:47 +03:00
port.h	net/mlx5e: Add support for reading connector type from PTYS	2017-06-08 14:12:00 +03:00
qp.h	net/mlx5e: Move and optimize query out of buffer function	2017-06-16 00:19:02 +03:00
srq.h	net/mlx5: Ensure SRQ physical address structure endianness	2016-10-30 15:43:10 +02:00
transobj.h
vport.h	net/mlx5: Push min-inline mode resolution helper into the core	2017-01-24 21:14:05 +02:00