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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a958df5dc3
There are a mix of function prototypes with and without extern in the kernel sources. Standardize on not using extern for function prototypes. Function prototypes don't need to be written with extern. extern is assumed by the compiler. Its use is as unnecessary as using auto to declare automatic/local variables in a block. Signed-off-by: Joe Perches <joe@perches.com>
232 lines
6.3 KiB
C
232 lines
6.3 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2013 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92C_PHY_H__
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#define __RTL92C_PHY_H__
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/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
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#define MAX_TX_COUNT 4
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#define MAX_PRECMD_CNT 16
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#define MAX_RFDEPENDCMD_CNT 16
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#define MAX_POSTCMD_CNT 16
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#define MAX_DOZE_WAITING_TIMES_9x 64
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#define RT_CANNOT_IO(hw) false
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#define HIGHPOWER_RADIOA_ARRAYLEN 22
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#define IQK_ADDA_REG_NUM 16
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#define IQK_BB_REG_NUM 9
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 10
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#define IDX_MAP 15
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#define APK_BB_REG_NUM 5
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#define APK_AFE_REG_NUM 16
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#define APK_CURVE_REG_NUM 4
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#define PATH_NUM 2
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50
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#define ANTENNADIVERSITYVALUE 0x80
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define RESET_CNT_LIMIT 3
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#define IQK_ADDA_REG_NUM 16
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#define IQK_MAC_REG_NUM 4
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#define RF6052_MAX_PATH 2
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#define CT_OFFSET_MAC_ADDR 0X16
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#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
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#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
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#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
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#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
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#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
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#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
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#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
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#define CT_OFFSET_CHANNEL_PLAH 0x75
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#define CT_OFFSET_THERMAL_METER 0x78
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#define CT_OFFSET_RF_OPTION 0x79
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#define CT_OFFSET_VERSION 0x7E
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#define CT_OFFSET_CUSTOMER_ID 0x7F
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#define RTL92C_MAX_PATH_NUM 2
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enum swchnlcmd_id {
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CMDID_END,
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CMDID_SET_TXPOWEROWER_LEVEL,
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CMDID_BBREGWRITE10,
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CMDID_WRITEPORT_ULONG,
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CMDID_WRITEPORT_USHORT,
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CMDID_WRITEPORT_UCHAR,
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CMDID_RF_WRITEREG,
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};
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struct swchnlcmd {
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enum swchnlcmd_id cmdid;
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u32 para1;
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u32 para2;
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u32 msdelay;
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};
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enum hw90_block_e {
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4,
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};
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enum baseband_config_type {
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BASEBAND_CONFIG_PHY_REG = 0,
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BASEBAND_CONFIG_AGC_TAB = 1,
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};
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enum ra_offset_area {
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RA_OFFSET_LEGACY_OFDM1,
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RA_OFFSET_LEGACY_OFDM2,
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RA_OFFSET_HT_OFDM1,
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RA_OFFSET_HT_OFDM2,
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RA_OFFSET_HT_OFDM3,
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RA_OFFSET_HT_OFDM4,
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RA_OFFSET_HT_CCK,
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};
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enum antenna_path {
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ANTENNA_NONE,
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ANTENNA_D,
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ANTENNA_C,
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ANTENNA_CD,
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ANTENNA_B,
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ANTENNA_BD,
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ANTENNA_BC,
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ANTENNA_BCD,
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ANTENNA_A,
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ANTENNA_AD,
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ANTENNA_AC,
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ANTENNA_ACD,
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ANTENNA_AB,
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ANTENNA_ABD,
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ANTENNA_ABC,
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ANTENNA_ABCD
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};
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struct r_antenna_select_ofdm {
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 ofdm_txsc:2;
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u32 reserved:2;
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};
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struct r_antenna_select_cck {
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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};
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struct efuse_contents {
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u8 mac_addr[ETH_ALEN];
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u8 cck_tx_power_idx[6];
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u8 ht40_1s_tx_power_idx[6];
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u8 ht40_2s_tx_power_idx_diff[3];
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u8 ht20_tx_power_idx_diff[3];
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u8 ofdm_tx_power_idx_diff[3];
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u8 ht40_max_power_offset[3];
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u8 ht20_max_power_offset[3];
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u8 channel_plan;
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u8 thermal_meter;
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u8 rf_option[5];
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u8 version;
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u8 oem_id;
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u8 regulatory;
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};
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struct tx_power_struct {
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u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 legacy_ht_txpowerdiff;
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u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
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u8 pwrgroup_cnt;
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u32 mcs_original_offset[4][16];
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};
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enum _ANT_DIV_TYPE {
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NO_ANTDIV = 0xFF,
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CG_TRX_HW_ANTDIV = 0x01,
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CGCS_RX_HW_ANTDIV = 0x02,
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FIXED_HW_ANTDIV = 0x03,
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CG_TRX_SMART_ANTDIV = 0x04,
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CGCS_RX_SW_ANTDIV = 0x05,
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};
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u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
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void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
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u32 data);
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u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
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u32 regaddr, u32 bitmask);
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void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
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u32 regaddr, u32 bitmask, u32 data);
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bool rtl88e_phy_mac_config(struct ieee80211_hw *hw);
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bool rtl88e_phy_bb_config(struct ieee80211_hw *hw);
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bool rtl88e_phy_rf_config(struct ieee80211_hw *hw);
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void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
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void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel);
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void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
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void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
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void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
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void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
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enum nl80211_channel_type ch_type);
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void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
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u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
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void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
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void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
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void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
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bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
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enum radio_path rfpath);
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bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
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bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
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enum rf_pwrstate rfpwr_state);
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#endif
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