mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 05:17:55 +07:00
a91be22c92
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
606 lines
17 KiB
C
606 lines
17 KiB
C
/*
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* r8a7778 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/dma-rcar-hpbdma.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/phy.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <linux/dma-mapping.h>
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#include <mach/irqs.h>
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#include <mach/r8a7778.h>
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#include <mach/common.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/cache-l2x0.h>
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/* SCIF */
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#define SCIF_INFO(baseaddr, irq) \
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{ \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
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.scbrr_algo_id = SCBRR_ALGO_2, \
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.type = PORT_SCIF, \
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.irqs = SCIx_IRQ_MUXED(irq), \
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}
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static struct plat_sci_port scif_platform_data[] __initdata = {
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SCIF_INFO(0xffe40000, gic_iid(0x66)),
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SCIF_INFO(0xffe41000, gic_iid(0x67)),
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SCIF_INFO(0xffe42000, gic_iid(0x68)),
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SCIF_INFO(0xffe43000, gic_iid(0x69)),
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SCIF_INFO(0xffe44000, gic_iid(0x6a)),
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SCIF_INFO(0xffe45000, gic_iid(0x6b)),
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};
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/* TMU */
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static struct resource sh_tmu0_resources[] __initdata = {
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DEFINE_RES_MEM(0xffd80008, 12),
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DEFINE_RES_IRQ(gic_iid(0x40)),
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};
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static struct sh_timer_config sh_tmu0_platform_data __initdata = {
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.name = "TMU00",
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.channel_offset = 0x4,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource sh_tmu1_resources[] __initdata = {
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DEFINE_RES_MEM(0xffd80014, 12),
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DEFINE_RES_IRQ(gic_iid(0x41)),
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};
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static struct sh_timer_config sh_tmu1_platform_data __initdata = {
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.name = "TMU01",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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#define r8a7778_register_tmu(idx) \
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platform_device_register_resndata( \
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&platform_bus, "sh_tmu", idx, \
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sh_tmu##idx##_resources, \
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ARRAY_SIZE(sh_tmu##idx##_resources), \
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&sh_tmu##idx##_platform_data, \
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sizeof(sh_tmu##idx##_platform_data))
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int r8a7778_usb_phy_power(bool enable)
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{
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static struct usb_phy *phy = NULL;
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int ret = 0;
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if (!phy)
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phy = usb_get_phy(USB_PHY_TYPE_USB2);
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if (IS_ERR(phy)) {
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pr_err("kernel doesn't have usb phy driver\n");
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return PTR_ERR(phy);
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}
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if (enable)
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ret = usb_phy_init(phy);
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else
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usb_phy_shutdown(phy);
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return ret;
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}
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/* USB */
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static int usb_power_on(struct platform_device *pdev)
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{
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int ret = r8a7778_usb_phy_power(true);
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if (ret)
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return ret;
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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return 0;
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}
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static void usb_power_off(struct platform_device *pdev)
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{
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if (r8a7778_usb_phy_power(false))
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return;
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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}
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static int ehci_init_internal_buffer(struct usb_hcd *hcd)
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{
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/*
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* Below are recommended values from the datasheet;
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* see [USB :: Setting of EHCI Internal Buffer].
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*/
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/* EHCI IP internal buffer setting */
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iowrite32(0x00ff0040, hcd->regs + 0x0094);
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/* EHCI IP internal buffer enable */
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iowrite32(0x00000001, hcd->regs + 0x009C);
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return 0;
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}
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static struct usb_ehci_pdata ehci_pdata __initdata = {
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.power_on = usb_power_on,
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.power_off = usb_power_off,
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.power_suspend = usb_power_off,
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.pre_setup = ehci_init_internal_buffer,
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};
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static struct resource ehci_resources[] __initdata = {
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DEFINE_RES_MEM(0xffe70000, 0x400),
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DEFINE_RES_IRQ(gic_iid(0x4c)),
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};
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static struct usb_ohci_pdata ohci_pdata __initdata = {
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.power_on = usb_power_on,
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.power_off = usb_power_off,
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.power_suspend = usb_power_off,
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};
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static struct resource ohci_resources[] __initdata = {
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DEFINE_RES_MEM(0xffe70400, 0x400),
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DEFINE_RES_IRQ(gic_iid(0x4c)),
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};
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#define USB_PLATFORM_INFO(hci) \
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static struct platform_device_info hci##_info __initdata = { \
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.parent = &platform_bus, \
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.name = #hci "-platform", \
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.id = -1, \
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.res = hci##_resources, \
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.num_res = ARRAY_SIZE(hci##_resources), \
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.data = &hci##_pdata, \
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.size_data = sizeof(hci##_pdata), \
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.dma_mask = DMA_BIT_MASK(32), \
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}
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USB_PLATFORM_INFO(ehci);
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USB_PLATFORM_INFO(ohci);
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/* PFC/GPIO */
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static struct resource pfc_resources[] __initdata = {
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DEFINE_RES_MEM(0xfffc0000, 0x118),
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};
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#define R8A7778_GPIO(idx) \
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static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
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DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
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DEFINE_RES_IRQ(gic_iid(0x87)), \
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}; \
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\
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static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
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.gpio_base = 32 * (idx), \
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.irq_base = GPIO_IRQ_BASE(idx), \
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.number_of_pins = 32, \
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.pctl_name = "pfc-r8a7778", \
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}
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R8A7778_GPIO(0);
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R8A7778_GPIO(1);
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R8A7778_GPIO(2);
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R8A7778_GPIO(3);
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R8A7778_GPIO(4);
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#define r8a7778_register_gpio(idx) \
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platform_device_register_resndata( \
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&platform_bus, "gpio_rcar", idx, \
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r8a7778_gpio##idx##_resources, \
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ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
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&r8a7778_gpio##idx##_platform_data, \
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sizeof(r8a7778_gpio##idx##_platform_data))
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void __init r8a7778_pinmux_init(void)
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{
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platform_device_register_simple(
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"pfc-r8a7778", -1,
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pfc_resources,
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ARRAY_SIZE(pfc_resources));
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r8a7778_register_gpio(0);
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r8a7778_register_gpio(1);
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r8a7778_register_gpio(2);
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r8a7778_register_gpio(3);
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r8a7778_register_gpio(4);
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};
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/* I2C */
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static struct resource i2c_resources[] __initdata = {
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/* I2C0 */
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DEFINE_RES_MEM(0xffc70000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x63)),
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/* I2C1 */
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DEFINE_RES_MEM(0xffc71000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x6e)),
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/* I2C2 */
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DEFINE_RES_MEM(0xffc72000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x6c)),
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/* I2C3 */
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DEFINE_RES_MEM(0xffc73000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x6d)),
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};
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static void __init r8a7778_register_i2c(int id)
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{
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BUG_ON(id < 0 || id > 3);
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platform_device_register_simple(
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"i2c-rcar", id,
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i2c_resources + (2 * id), 2);
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}
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/* HSPI */
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static struct resource hspi_resources[] __initdata = {
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/* HSPI0 */
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DEFINE_RES_MEM(0xfffc7000, 0x18),
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DEFINE_RES_IRQ(gic_iid(0x5f)),
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/* HSPI1 */
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DEFINE_RES_MEM(0xfffc8000, 0x18),
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DEFINE_RES_IRQ(gic_iid(0x74)),
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/* HSPI2 */
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DEFINE_RES_MEM(0xfffc6000, 0x18),
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DEFINE_RES_IRQ(gic_iid(0x75)),
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};
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static void __init r8a7778_register_hspi(int id)
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{
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BUG_ON(id < 0 || id > 2);
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platform_device_register_simple(
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"sh-hspi", id,
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hspi_resources + (2 * id), 2);
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}
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void __init r8a7778_add_dt_devices(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
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if (base) {
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/*
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* Early BRESP enable, Shared attribute override enable, 64K*16way
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* don't call iounmap(base)
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*/
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l2x0_init(base, 0x40470000, 0x82000fff);
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}
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#endif
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for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
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platform_device_register_data(&platform_bus, "sh-sci", i,
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&scif_platform_data[i],
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sizeof(struct plat_sci_port));
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r8a7778_register_tmu(0);
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r8a7778_register_tmu(1);
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}
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/* HPB-DMA */
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/* Asynchronous mode register (ASYNCMDR) bits */
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#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */
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#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */
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#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
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#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */
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#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
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#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
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#define HPBDMA_SSI(_id) \
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{ \
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.id = HPBDMA_SLAVE_SSI## _id ##_TX, \
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.addr = 0xffd91008 + (_id * 0x40), \
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.dcr = HPB_DMAE_DCR_CT | \
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HPB_DMAE_DCR_DIP | \
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HPB_DMAE_DCR_SPDS_32BIT | \
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HPB_DMAE_DCR_DMDL | \
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HPB_DMAE_DCR_DPDS_32BIT, \
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.port = _id + (_id << 8), \
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.dma_ch = (28 + _id), \
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}, { \
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.id = HPBDMA_SLAVE_SSI## _id ##_RX, \
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.addr = 0xffd9100c + (_id * 0x40), \
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.dcr = HPB_DMAE_DCR_CT | \
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HPB_DMAE_DCR_DIP | \
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HPB_DMAE_DCR_SMDL | \
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HPB_DMAE_DCR_SPDS_32BIT | \
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HPB_DMAE_DCR_DPDS_32BIT, \
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.port = _id + (_id << 8), \
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.dma_ch = (28 + _id), \
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}
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#define HPBDMA_HPBIF(_id) \
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{ \
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.id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
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.addr = 0xffda0000 + (_id * 0x1000), \
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.dcr = HPB_DMAE_DCR_CT | \
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HPB_DMAE_DCR_DIP | \
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HPB_DMAE_DCR_SPDS_32BIT | \
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HPB_DMAE_DCR_DMDL | \
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HPB_DMAE_DCR_DPDS_32BIT, \
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.port = 0x1111, \
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.dma_ch = (28 + _id), \
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}, { \
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.id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
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.addr = 0xffda0000 + (_id * 0x1000), \
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.dcr = HPB_DMAE_DCR_CT | \
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HPB_DMAE_DCR_DIP | \
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HPB_DMAE_DCR_SMDL | \
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HPB_DMAE_DCR_SPDS_32BIT | \
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HPB_DMAE_DCR_DPDS_32BIT, \
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.port = 0x1111, \
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.dma_ch = (28 + _id), \
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}
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static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
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{
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.id = HPBDMA_SLAVE_SDHI0_TX,
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.addr = 0xffe4c000 + 0x30,
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.dcr = HPB_DMAE_DCR_SPDS_16BIT |
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HPB_DMAE_DCR_DMDL |
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HPB_DMAE_DCR_DPDS_16BIT,
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.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
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HPB_DMAE_ASYNCRSTR_ASRST22 |
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HPB_DMAE_ASYNCRSTR_ASRST23,
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.mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
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.mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
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.port = 0x0D0C,
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.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
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.dma_ch = 21,
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}, {
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.id = HPBDMA_SLAVE_SDHI0_RX,
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.addr = 0xffe4c000 + 0x30,
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.dcr = HPB_DMAE_DCR_SMDL |
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HPB_DMAE_DCR_SPDS_16BIT |
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HPB_DMAE_DCR_DPDS_16BIT,
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.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
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HPB_DMAE_ASYNCRSTR_ASRST22 |
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HPB_DMAE_ASYNCRSTR_ASRST23,
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.mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
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.mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
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.port = 0x0D0C,
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.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
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.dma_ch = 22,
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},
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HPBDMA_SSI(0),
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HPBDMA_SSI(1),
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HPBDMA_SSI(2),
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HPBDMA_SSI(3),
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HPBDMA_SSI(4),
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HPBDMA_SSI(5),
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HPBDMA_SSI(6),
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HPBDMA_SSI(7),
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HPBDMA_SSI(8),
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HPBDMA_HPBIF(0),
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HPBDMA_HPBIF(1),
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HPBDMA_HPBIF(2),
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HPBDMA_HPBIF(3),
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HPBDMA_HPBIF(4),
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HPBDMA_HPBIF(5),
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HPBDMA_HPBIF(6),
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HPBDMA_HPBIF(7),
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HPBDMA_HPBIF(8),
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};
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static const struct hpb_dmae_channel hpb_dmae_channels[] = {
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HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
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HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
|
|
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
|
|
};
|
|
|
|
static struct hpb_dmae_pdata dma_platform_data __initdata = {
|
|
.slaves = hpb_dmae_slaves,
|
|
.num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
|
|
.channels = hpb_dmae_channels,
|
|
.num_channels = ARRAY_SIZE(hpb_dmae_channels),
|
|
.ts_shift = {
|
|
[XMIT_SZ_8BIT] = 0,
|
|
[XMIT_SZ_16BIT] = 1,
|
|
[XMIT_SZ_32BIT] = 2,
|
|
},
|
|
.num_hw_channels = 39,
|
|
};
|
|
|
|
static struct resource hpb_dmae_resources[] __initdata = {
|
|
/* Channel registers */
|
|
DEFINE_RES_MEM(0xffc08000, 0x1000),
|
|
/* Common registers */
|
|
DEFINE_RES_MEM(0xffc09000, 0x170),
|
|
/* Asynchronous reset registers */
|
|
DEFINE_RES_MEM(0xffc00300, 4),
|
|
/* Asynchronous mode registers */
|
|
DEFINE_RES_MEM(0xffc00400, 4),
|
|
/* IRQ for DMA channels */
|
|
DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
|
|
};
|
|
|
|
static void __init r8a7778_register_hpb_dmae(void)
|
|
{
|
|
platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
|
|
hpb_dmae_resources,
|
|
ARRAY_SIZE(hpb_dmae_resources),
|
|
&dma_platform_data,
|
|
sizeof(dma_platform_data));
|
|
}
|
|
|
|
void __init r8a7778_add_standard_devices(void)
|
|
{
|
|
r8a7778_add_dt_devices();
|
|
r8a7778_register_i2c(0);
|
|
r8a7778_register_i2c(1);
|
|
r8a7778_register_i2c(2);
|
|
r8a7778_register_i2c(3);
|
|
r8a7778_register_hspi(0);
|
|
r8a7778_register_hspi(1);
|
|
r8a7778_register_hspi(2);
|
|
|
|
r8a7778_register_hpb_dmae();
|
|
}
|
|
|
|
void __init r8a7778_init_late(void)
|
|
{
|
|
platform_device_register_full(&ehci_info);
|
|
platform_device_register_full(&ohci_info);
|
|
}
|
|
|
|
static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
|
|
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
|
|
.sense_bitfield_width = 2,
|
|
};
|
|
|
|
static struct resource irqpin_resources[] __initdata = {
|
|
DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
|
|
DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
|
|
DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
|
|
DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
|
|
DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
|
|
DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
|
|
DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
|
|
DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
|
|
DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
|
|
};
|
|
|
|
void __init r8a7778_init_irq_extpin_dt(int irlm)
|
|
{
|
|
void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
|
|
unsigned long tmp;
|
|
|
|
if (!icr0) {
|
|
pr_warn("r8a7778: unable to setup external irq pin mode\n");
|
|
return;
|
|
}
|
|
|
|
tmp = ioread32(icr0);
|
|
if (irlm)
|
|
tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
|
|
else
|
|
tmp &= ~(1 << 23); /* IRL mode - not supported */
|
|
tmp |= (1 << 21); /* LVLMODE = 1 */
|
|
iowrite32(tmp, icr0);
|
|
iounmap(icr0);
|
|
}
|
|
|
|
void __init r8a7778_init_irq_extpin(int irlm)
|
|
{
|
|
r8a7778_init_irq_extpin_dt(irlm);
|
|
if (irlm)
|
|
platform_device_register_resndata(
|
|
&platform_bus, "renesas_intc_irqpin", -1,
|
|
irqpin_resources, ARRAY_SIZE(irqpin_resources),
|
|
&irqpin_platform_data, sizeof(irqpin_platform_data));
|
|
}
|
|
|
|
void __init r8a7778_init_delay(void)
|
|
{
|
|
shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
|
|
}
|
|
|
|
#ifdef CONFIG_USE_OF
|
|
#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
|
|
#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
|
|
|
|
#define INT2NTSR0 0x00018 /* 0xfe700018 */
|
|
#define INT2NTSR1 0x0002c /* 0xfe70002c */
|
|
void __init r8a7778_init_irq_dt(void)
|
|
{
|
|
void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
|
|
|
|
BUG_ON(!base);
|
|
|
|
irqchip_init();
|
|
|
|
/* route all interrupts to ARM */
|
|
__raw_writel(0x73ffffff, base + INT2NTSR0);
|
|
__raw_writel(0xffffffff, base + INT2NTSR1);
|
|
|
|
/* unmask all known interrupts in INTCS2 */
|
|
__raw_writel(0x08330773, base + INT2SMSKCR0);
|
|
__raw_writel(0x00311110, base + INT2SMSKCR1);
|
|
|
|
iounmap(base);
|
|
}
|
|
|
|
static const char *r8a7778_compat_dt[] __initdata = {
|
|
"renesas,r8a7778",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
|
|
.init_early = r8a7778_init_delay,
|
|
.init_irq = r8a7778_init_irq_dt,
|
|
.dt_compat = r8a7778_compat_dt,
|
|
.init_late = r8a7778_init_late,
|
|
MACHINE_END
|
|
|
|
#endif /* CONFIG_USE_OF */
|