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367d2b0cb1
The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx SinA33 has its cpu-supply property set in the cpu DT node. Therefore, CPUfreq knows how to handle the regulator in charge of the CPU and can adjust its voltage to match the OPP. Add these two CPU frequencies to the CPU OPP table of the Sinlinx SinA33. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
291 lines
5.9 KiB
Plaintext
291 lines
5.9 KiB
Plaintext
/*
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* Copyright 2015 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "sun8i-a33.dtsi"
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#include "sunxi-common-regulators.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Sinlinx SinA33";
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compatible = "sinlinx,sina33", "allwinner,sun8i-a33";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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panel {
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compatible = "netron-dy,e231732";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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panel_input: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_out_panel>;
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};
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};
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};
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};
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&codec {
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <®_dcdc3>;
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};
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&cpu0_opp_table {
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opp@1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <1320000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1320000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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};
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&de {
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status = "okay";
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};
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&dai {
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status = "okay";
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};
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&ehci0 {
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status = "okay";
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};
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&lradc {
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vref-supply = <®_dcdc1>;
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status = "okay";
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button@200 {
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label = "Volume Up";
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linux,code = <KEY_VOLUMEUP>;
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channel = <0>;
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voltage = <191011>;
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};
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button@400 {
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label = "Volume Down";
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linux,code = <KEY_VOLUMEDOWN>;
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channel = <0>;
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voltage = <391304>;
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};
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button@600 {
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label = "Home";
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linux,code = <KEY_HOME>;
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channel = <0>;
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voltage = <600000>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
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vmmc-supply = <®_dcdc1>;
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bus-width = <4>;
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cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
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cd-inverted;
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status = "okay";
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};
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_8bit_pins>;
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vmmc-supply = <®_dcdc1>;
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bus-width = <8>;
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non-removable;
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cap-mmc-hw-reset;
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status = "okay";
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};
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&mmc2_8bit_pins {
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/* Increase drive strength for DDR modes */
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drive-strength = <40>;
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/* eMMC is missing pull-ups */
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bias-pull-up;
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};
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&ohci0 {
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status = "okay";
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};
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&pio {
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mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
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pins = "PB4";
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function = "gpio_in";
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bias-pull-up;
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};
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};
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&r_rsb {
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status = "okay";
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axp22x: pmic@3a3 {
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compatible = "x-powers,axp223";
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reg = <0x3a3>;
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interrupt-parent = <&nmi_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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eldoin-supply = <®_dcdc1>;
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};
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};
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#include "axp223.dtsi"
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&ac_power_supply {
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status = "okay";
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};
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®_aldo1 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-io";
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};
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®_aldo2 {
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regulator-always-on;
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regulator-min-microvolt = <2350000>;
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regulator-max-microvolt = <2650000>;
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regulator-name = "vdd-dll";
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};
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®_aldo3 {
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regulator-always-on;
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc-pll-avcc";
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};
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®_dc5ldo {
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regulator-always-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "vdd-cpus";
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};
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®_dcdc1 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-3v0";
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};
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®_dcdc2 {
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regulator-always-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "vdd-sys";
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};
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®_dcdc3 {
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regulator-always-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "vdd-cpu";
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};
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®_dcdc5 {
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regulator-always-on;
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-name = "vcc-dram";
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};
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®_rtc_ldo {
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regulator-name = "vcc-rtc";
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};
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&sound {
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status = "okay";
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};
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&tcon0 {
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_rgb666_pins>;
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status = "okay";
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};
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&tcon0_out {
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tcon0_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_input>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins_b>;
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status = "okay";
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};
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&usb_otg {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbphy {
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status = "okay";
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usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */
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};
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