Sonika Jindal a8f3ef6197 drm/i915/skl: Add support for edp 1.4 intermediate frequencies ... eDp 1.4 supports custom frequencies. Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and 4.32 GHz along with usual LBR, HBR and HBR2 frequencies. Read sink supported frequencies and get common frequencies from sink and source and use these for link training. v2: Rebased, removed calculation of min_clock since for edp it is taken as max_clock (as per comment). v3: Keeping single array for link rates (Satheesh) v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh) v5: Some minor nits (Ville) v6: Keeping separate arrays for source and sink rates (Ville) v7: Remove redundant setting of DP_LINK_BW_SET to 0 (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-03-17 22:29:57 +01:00
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drm	drm/i915/skl: Add support for edp 1.4 intermediate frequencies	2015-03-17 22:29:57 +01:00
host1x	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00
ipu-v3	gpu: ipu-v3: do not divide by zero if the pixel clock is too large	2015-02-23 17:18:59 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00