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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6b88a32c7a
With ARM64_SW_TTBR0_PAN enabled, the exception entry code checks the active ASID to decide whether user access was enabled (non-zero ASID) when the exception was taken. On return from exception, if user access was previously disabled, it re-instates TTBR0_EL1 from the per-thread saved value (updated in switch_mm() or efi_set_pgd()). Commit7655abb953("arm64: mm: Move ASID from TTBR0 to TTBR1") makes a TTBR0_EL1 + ASID switching non-atomic. Subsequently, commit27a921e757("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN") changes the __uaccess_ttbr0_disable() function and asm macro to first write the reserved TTBR0_EL1 followed by the ASID=0 update in TTBR1_EL1. If an exception occurs between these two, the exception return code will re-instate a valid TTBR0_EL1. Similar scenario can happen in cpu_switch_mm() between setting the reserved TTBR0_EL1 and the ASID update in cpu_do_switch_mm(). This patch reverts the entry.S check for ASID == 0 to TTBR0_EL1 and disables the interrupts around the TTBR0_EL1 and ASID switching code in __uaccess_ttbr0_disable(). It also ensures that, when returning from the EFI runtime services, efi_set_pgd() doesn't leave a non-zero ASID in TTBR1_EL1 by using uaccess_ttbr0_{enable,disable}. The accesses to current_thread_info()->ttbr0 are updated to use READ_ONCE/WRITE_ONCE. As a safety measure, __uaccess_ttbr0_enable() always masks out any existing non-zero ASID TTBR1_EL1 before writing in the new ASID. Fixes:27a921e757("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN") Acked-by: Will Deacon <will.deacon@arm.com> Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: James Morse <james.morse@arm.com> Tested-by: James Morse <james.morse@arm.com> Co-developed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
113 lines
3.6 KiB
ArmAsm
113 lines
3.6 KiB
ArmAsm
/******************************************************************************
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* hypercall.S
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*
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* Xen hypercall wrappers
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*
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* Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation; or, when distributed
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* separately from the Linux kernel or incorporated into other
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* software packages, subject to the following license:
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this source file (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy, modify,
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* merge, publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/*
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* The Xen hypercall calling convention is very similar to the procedure
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* call standard for the ARM 64-bit architecture: the first parameter is
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* passed in x0, the second in x1, the third in x2, the fourth in x3 and
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* the fifth in x4.
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*
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* The hypercall number is passed in x16.
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*
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* The return value is in x0.
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*
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* The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
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* hypercall tag.
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*
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* Parameter structs passed to hypercalls are laid out according to
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* the ARM 64-bit EABI standard.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-uaccess.h>
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#include <xen/interface/xen.h>
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#define XEN_IMM 0xEA1
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#define HYPERCALL_SIMPLE(hypercall) \
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ENTRY(HYPERVISOR_##hypercall) \
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mov x16, #__HYPERVISOR_##hypercall; \
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hvc XEN_IMM; \
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ret; \
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ENDPROC(HYPERVISOR_##hypercall)
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#define HYPERCALL0 HYPERCALL_SIMPLE
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#define HYPERCALL1 HYPERCALL_SIMPLE
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#define HYPERCALL2 HYPERCALL_SIMPLE
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#define HYPERCALL3 HYPERCALL_SIMPLE
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#define HYPERCALL4 HYPERCALL_SIMPLE
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#define HYPERCALL5 HYPERCALL_SIMPLE
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.text
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HYPERCALL2(xen_version);
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HYPERCALL3(console_io);
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HYPERCALL3(grant_table_op);
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HYPERCALL2(sched_op);
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HYPERCALL2(event_channel_op);
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HYPERCALL2(hvm_op);
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HYPERCALL2(memory_op);
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HYPERCALL2(physdev_op);
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HYPERCALL3(vcpu_op);
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HYPERCALL1(tmem_op);
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HYPERCALL1(platform_op_raw);
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HYPERCALL2(multicall);
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HYPERCALL2(vm_assist);
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HYPERCALL3(dm_op);
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ENTRY(privcmd_call)
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mov x16, x0
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mov x0, x1
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mov x1, x2
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mov x2, x3
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mov x3, x4
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mov x4, x5
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/*
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* Privcmd calls are issued by the userspace. The kernel needs to
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* enable access to TTBR0_EL1 as the hypervisor would issue stage 1
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* translations to user memory via AT instructions. Since AT
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* instructions are not affected by the PAN bit (ARMv8.1), we only
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* need the explicit uaccess_enable/disable if the TTBR0 PAN emulation
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* is enabled (it implies that hardware UAO and PAN disabled).
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*/
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uaccess_ttbr0_enable x6, x7, x8
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hvc XEN_IMM
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/*
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* Disable userspace access from kernel once the hyp call completed.
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*/
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uaccess_ttbr0_disable x6, x7
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ret
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ENDPROC(privcmd_call);
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