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2a594d4ccf
The debug IST stack is actually two separate debug stacks to handle #DB
recursion. This is required because the CPU starts always at top of stack
on exception entry, which means on #DB recursion the second #DB would
overwrite the stack of the first.
The low level entry code therefore adjusts the top of stack on entry so a
secondary #DB starts from a different stack page. But the stack pages are
adjacent without a guard page between them.
Split the debug stack into 3 stacks which are separated by guard pages. The
3rd stack is never mapped into the cpu_entry_area and is only there to
catch triple #DB nesting:
--- top of DB_stack <- Initial stack
--- end of DB_stack
guard page
--- top of DB1_stack <- Top of stack after entering first #DB
--- end of DB1_stack
guard page
--- top of DB2_stack <- Top of stack after entering second #DB
--- end of DB2_stack
guard page
If DB2 would not act as the final guard hole, a second #DB would point the
top of #DB stack to the stack below #DB1 which would be valid and not catch
the not so desired triple nesting.
The backing store does not allocate any memory for DB2 and its guard page
as it is not going to be mapped into the cpu_entry_area.
- Adjust the low level entry code so it adjusts top of #DB with the offset
between the stacks instead of exception stack size.
- Make the dumpstack code aware of the new stacks.
- Adjust the in_debug_stack() implementation and move it into the NMI code
where it belongs. As this is NMI hotpath code, it just checks the full
area between top of DB_stack and bottom of DB1_stack without checking
for the guard page. That's correct because the NMI cannot hit a
stackpointer pointing to the guard page between DB and DB1 stack. Even
if it would, then the NMI operation still is unaffected, but the resume
of the debug exception on the topmost DB stack will crash by touching
the guard page.
[ bp: Make exception_stack_names static const char * const ]
Suggested-by: Andy Lutomirski <luto@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Baoquan He <bhe@redhat.com>
Cc: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Joerg Roedel <jroedel@suse.de>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: linux-doc@vger.kernel.org
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Qian Cai <cai@lca.pw>
Cc: Sean Christopherson <sean.j.christopherson@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190414160145.439944544@linutronix.de
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef _ASM_X86_CPU_ENTRY_AREA_H
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#define _ASM_X86_CPU_ENTRY_AREA_H
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#include <linux/percpu-defs.h>
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#include <asm/processor.h>
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#include <asm/intel_ds.h>
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#ifdef CONFIG_X86_64
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/* Macro to enforce the same ordering and stack sizes */
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#define ESTACKS_MEMBERS(guardsize, db2_holesize)\
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char DF_stack_guard[guardsize]; \
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char DF_stack[EXCEPTION_STKSZ]; \
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char NMI_stack_guard[guardsize]; \
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char NMI_stack[EXCEPTION_STKSZ]; \
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char DB2_stack_guard[guardsize]; \
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char DB2_stack[db2_holesize]; \
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char DB1_stack_guard[guardsize]; \
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char DB1_stack[EXCEPTION_STKSZ]; \
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char DB_stack_guard[guardsize]; \
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char DB_stack[EXCEPTION_STKSZ]; \
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char MCE_stack_guard[guardsize]; \
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char MCE_stack[EXCEPTION_STKSZ]; \
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char IST_top_guard[guardsize]; \
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/* The exception stacks' physical storage. No guard pages required */
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struct exception_stacks {
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ESTACKS_MEMBERS(0, 0)
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};
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/* The effective cpu entry area mapping with guard pages. */
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struct cea_exception_stacks {
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ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ)
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};
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/*
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* The exception stack ordering in [cea_]exception_stacks
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*/
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enum exception_stack_ordering {
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ESTACK_DF,
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ESTACK_NMI,
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ESTACK_DB2,
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ESTACK_DB1,
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ESTACK_DB,
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ESTACK_MCE,
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N_EXCEPTION_STACKS
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};
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#define CEA_ESTACK_SIZE(st) \
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sizeof(((struct cea_exception_stacks *)0)->st## _stack)
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#define CEA_ESTACK_BOT(ceastp, st) \
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((unsigned long)&(ceastp)->st## _stack)
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#define CEA_ESTACK_TOP(ceastp, st) \
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(CEA_ESTACK_BOT(ceastp, st) + CEA_ESTACK_SIZE(st))
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#define CEA_ESTACK_OFFS(st) \
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offsetof(struct cea_exception_stacks, st## _stack)
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#define CEA_ESTACK_PAGES \
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(sizeof(struct cea_exception_stacks) / PAGE_SIZE)
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#endif
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/*
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* cpu_entry_area is a percpu region that contains things needed by the CPU
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* and early entry/exit code. Real types aren't used for all fields here
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* to avoid circular header dependencies.
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*
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* Every field is a virtual alias of some other allocated backing store.
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* There is no direct allocation of a struct cpu_entry_area.
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*/
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struct cpu_entry_area {
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char gdt[PAGE_SIZE];
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/*
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* The GDT is just below entry_stack and thus serves (on x86_64) as
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* a a read-only guard page.
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*/
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struct entry_stack_page entry_stack_page;
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/*
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* On x86_64, the TSS is mapped RO. On x86_32, it's mapped RW because
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* we need task switches to work, and task switches write to the TSS.
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*/
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struct tss_struct tss;
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#ifdef CONFIG_X86_64
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/*
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* Exception stacks used for IST entries with guard pages.
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*/
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struct cea_exception_stacks estacks;
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#endif
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#ifdef CONFIG_CPU_SUP_INTEL
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/*
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* Per CPU debug store for Intel performance monitoring. Wastes a
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* full page at the moment.
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*/
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struct debug_store cpu_debug_store;
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/*
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* The actual PEBS/BTS buffers must be mapped to user space
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* Reserve enough fixmap PTEs.
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*/
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struct debug_store_buffers cpu_debug_buffers;
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#endif
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};
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#define CPU_ENTRY_AREA_SIZE (sizeof(struct cpu_entry_area))
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#define CPU_ENTRY_AREA_TOT_SIZE (CPU_ENTRY_AREA_SIZE * NR_CPUS)
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DECLARE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
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DECLARE_PER_CPU(struct cea_exception_stacks *, cea_exception_stacks);
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extern void setup_cpu_entry_areas(void);
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extern void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags);
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#define CPU_ENTRY_AREA_RO_IDT CPU_ENTRY_AREA_BASE
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#define CPU_ENTRY_AREA_PER_CPU (CPU_ENTRY_AREA_RO_IDT + PAGE_SIZE)
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#define CPU_ENTRY_AREA_RO_IDT_VADDR ((void *)CPU_ENTRY_AREA_RO_IDT)
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#define CPU_ENTRY_AREA_MAP_SIZE \
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(CPU_ENTRY_AREA_PER_CPU + CPU_ENTRY_AREA_TOT_SIZE - CPU_ENTRY_AREA_BASE)
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extern struct cpu_entry_area *get_cpu_entry_area(int cpu);
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static inline struct entry_stack *cpu_entry_stack(int cpu)
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{
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return &get_cpu_entry_area(cpu)->entry_stack_page.stack;
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}
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#define __this_cpu_ist_top_va(name) \
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CEA_ESTACK_TOP(__this_cpu_read(cea_exception_stacks), name)
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#endif
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