mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 01:30:52 +07:00
58657d189a
* 'clk-hw-register' (early part): clk: fixed-rate: Add hw based registration APIs clk: gpio: Add hw based registration APIs clk: composite: Add hw based registration APIs clk: fractional-divider: Add hw based registration APIs clk: fixed-factor: Add hw based registration APIs clk: mux: Add hw based registration APIs clk: gate: Add hw based registration APIs clk: divider: Add hw based registration APIs clkdev: Add clk_hw based registration APIs clk: Add clk_hw OF clk providers clk: Add {devm_}clk_hw_{register,unregister}() APIs clkdev: Remove clk_register_clkdevs()
358 lines
9.5 KiB
C
358 lines
9.5 KiB
C
/*
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* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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static u8 clk_composite_get_parent(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *mux_hw = composite->mux_hw;
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->get_parent(mux_hw);
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}
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static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *mux_hw = composite->mux_hw;
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->set_parent(mux_hw, index);
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}
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static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->recalc_rate(rate_hw, parent_rate);
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}
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static int clk_composite_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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struct clk_hw *mux_hw = composite->mux_hw;
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struct clk_hw *parent;
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unsigned long parent_rate;
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long tmp_rate, best_rate = 0;
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unsigned long rate_diff;
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unsigned long best_rate_diff = ULONG_MAX;
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long rate;
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int i;
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if (rate_hw && rate_ops && rate_ops->determine_rate) {
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->determine_rate(rate_hw, req);
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} else if (rate_hw && rate_ops && rate_ops->round_rate &&
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mux_hw && mux_ops && mux_ops->set_parent) {
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req->best_parent_hw = NULL;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
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parent = clk_hw_get_parent(mux_hw);
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req->best_parent_hw = parent;
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req->best_parent_rate = clk_hw_get_rate(parent);
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rate = rate_ops->round_rate(rate_hw, req->rate,
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&req->best_parent_rate);
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if (rate < 0)
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return rate;
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req->rate = rate;
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return 0;
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}
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for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
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parent = clk_hw_get_parent_by_index(mux_hw, i);
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if (!parent)
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continue;
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parent_rate = clk_hw_get_rate(parent);
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tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
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&parent_rate);
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if (tmp_rate < 0)
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continue;
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rate_diff = abs(req->rate - tmp_rate);
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if (!rate_diff || !req->best_parent_hw
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|| best_rate_diff > rate_diff) {
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req->best_parent_hw = parent;
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req->best_parent_rate = parent_rate;
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best_rate_diff = rate_diff;
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best_rate = tmp_rate;
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}
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if (!rate_diff)
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return 0;
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}
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req->rate = best_rate;
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return 0;
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} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->determine_rate(mux_hw, req);
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} else {
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pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
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return -EINVAL;
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}
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}
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static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->round_rate(rate_hw, rate, prate);
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}
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static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->set_rate(rate_hw, rate, parent_rate);
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}
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static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 index)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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struct clk_hw *mux_hw = composite->mux_hw;
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unsigned long temp_rate;
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__clk_hw_set_clk(rate_hw, hw);
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__clk_hw_set_clk(mux_hw, hw);
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temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
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if (temp_rate > rate) {
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rate_ops->set_rate(rate_hw, rate, parent_rate);
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mux_ops->set_parent(mux_hw, index);
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} else {
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mux_ops->set_parent(mux_hw, index);
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rate_ops->set_rate(rate_hw, rate, parent_rate);
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}
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return 0;
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}
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static int clk_composite_is_enabled(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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__clk_hw_set_clk(gate_hw, hw);
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return gate_ops->is_enabled(gate_hw);
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}
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static int clk_composite_enable(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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__clk_hw_set_clk(gate_hw, hw);
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return gate_ops->enable(gate_hw);
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}
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static void clk_composite_disable(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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__clk_hw_set_clk(gate_hw, hw);
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gate_ops->disable(gate_hw);
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}
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struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
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const char * const *parent_names, int num_parents,
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struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
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struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
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struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
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unsigned long flags)
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{
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struct clk_hw *hw;
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struct clk_init_data init;
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struct clk_composite *composite;
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struct clk_ops *clk_composite_ops;
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int ret;
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composite = kzalloc(sizeof(*composite), GFP_KERNEL);
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if (!composite)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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hw = &composite->hw;
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clk_composite_ops = &composite->ops;
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if (mux_hw && mux_ops) {
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if (!mux_ops->get_parent) {
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hw = ERR_PTR(-EINVAL);
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goto err;
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}
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composite->mux_hw = mux_hw;
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composite->mux_ops = mux_ops;
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clk_composite_ops->get_parent = clk_composite_get_parent;
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if (mux_ops->set_parent)
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clk_composite_ops->set_parent = clk_composite_set_parent;
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if (mux_ops->determine_rate)
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clk_composite_ops->determine_rate = clk_composite_determine_rate;
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}
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if (rate_hw && rate_ops) {
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if (!rate_ops->recalc_rate) {
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hw = ERR_PTR(-EINVAL);
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goto err;
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}
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clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
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if (rate_ops->determine_rate)
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clk_composite_ops->determine_rate =
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clk_composite_determine_rate;
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else if (rate_ops->round_rate)
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clk_composite_ops->round_rate =
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clk_composite_round_rate;
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/* .set_rate requires either .round_rate or .determine_rate */
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if (rate_ops->set_rate) {
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if (rate_ops->determine_rate || rate_ops->round_rate)
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clk_composite_ops->set_rate =
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clk_composite_set_rate;
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else
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WARN(1, "%s: missing round_rate op is required\n",
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__func__);
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}
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composite->rate_hw = rate_hw;
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composite->rate_ops = rate_ops;
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}
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if (mux_hw && mux_ops && rate_hw && rate_ops) {
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if (mux_ops->set_parent && rate_ops->set_rate)
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clk_composite_ops->set_rate_and_parent =
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clk_composite_set_rate_and_parent;
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}
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if (gate_hw && gate_ops) {
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if (!gate_ops->is_enabled || !gate_ops->enable ||
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!gate_ops->disable) {
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hw = ERR_PTR(-EINVAL);
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goto err;
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}
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composite->gate_hw = gate_hw;
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composite->gate_ops = gate_ops;
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clk_composite_ops->is_enabled = clk_composite_is_enabled;
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clk_composite_ops->enable = clk_composite_enable;
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clk_composite_ops->disable = clk_composite_disable;
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}
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init.ops = clk_composite_ops;
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composite->hw.init = &init;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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hw = ERR_PTR(ret);
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goto err;
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}
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if (composite->mux_hw)
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composite->mux_hw->clk = hw->clk;
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if (composite->rate_hw)
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composite->rate_hw->clk = hw->clk;
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if (composite->gate_hw)
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composite->gate_hw->clk = hw->clk;
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return hw;
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err:
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kfree(composite);
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return hw;
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}
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struct clk *clk_register_composite(struct device *dev, const char *name,
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const char * const *parent_names, int num_parents,
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struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
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struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
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struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
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unsigned long flags)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
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mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
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flags);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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void clk_unregister_composite(struct clk *clk)
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{
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struct clk_composite *composite;
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struct clk_hw *hw;
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hw = __clk_get_hw(clk);
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if (!hw)
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return;
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composite = to_clk_composite(hw);
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clk_unregister(clk);
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kfree(composite);
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}
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