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8cb7eff32c
The addition of PMR should not bypass the semantics of daifflags. When DA_F are set, I bit is also set as no interrupts (even of higher priority) is allowed. When DA_F are cleared, I bit is cleared and interrupt enabling/disabling goes through ICC_PMR_EL1. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (C) 2017 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_DAIFFLAGS_H
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#define __ASM_DAIFFLAGS_H
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#include <linux/irqflags.h>
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#include <asm/cpufeature.h>
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#define DAIF_PROCCTX 0
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#define DAIF_PROCCTX_NOIRQ PSR_I_BIT
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/* mask/save/unmask/restore all exceptions, including interrupts. */
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static inline void local_daif_mask(void)
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{
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asm volatile(
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"msr daifset, #0xf // local_daif_mask\n"
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:
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:
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: "memory");
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trace_hardirqs_off();
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}
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static inline unsigned long local_daif_save(void)
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{
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unsigned long flags;
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flags = read_sysreg(daif);
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if (system_uses_irq_prio_masking()) {
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/* If IRQs are masked with PMR, reflect it in the flags */
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if (read_sysreg_s(SYS_ICC_PMR_EL1) <= GIC_PRIO_IRQOFF)
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flags |= PSR_I_BIT;
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}
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local_daif_mask();
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return flags;
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}
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static inline void local_daif_restore(unsigned long flags)
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{
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bool irq_disabled = flags & PSR_I_BIT;
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if (!irq_disabled) {
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trace_hardirqs_on();
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if (system_uses_irq_prio_masking())
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arch_local_irq_enable();
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} else if (!(flags & PSR_A_BIT)) {
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/*
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* If interrupts are disabled but we can take
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* asynchronous errors, we can take NMIs
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*/
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if (system_uses_irq_prio_masking()) {
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flags &= ~PSR_I_BIT;
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/*
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* There has been concern that the write to daif
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* might be reordered before this write to PMR.
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* From the ARM ARM DDI 0487D.a, section D1.7.1
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* "Accessing PSTATE fields":
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* Writes to the PSTATE fields have side-effects on
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* various aspects of the PE operation. All of these
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* side-effects are guaranteed:
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* - Not to be visible to earlier instructions in
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* the execution stream.
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* - To be visible to later instructions in the
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* execution stream
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*
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* Also, writes to PMR are self-synchronizing, so no
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* interrupts with a lower priority than PMR is signaled
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* to the PE after the write.
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*
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* So we don't need additional synchronization here.
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*/
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arch_local_irq_disable();
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}
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}
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write_sysreg(flags, daif);
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if (irq_disabled)
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trace_hardirqs_off();
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}
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#endif
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