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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ff92b9dd92
Updating MPI headers to the latest version 2.6.7 to add support to the driver to detect the new 3816 and 3916 chip based controllers. Separate out firmware image data from mpi2_ioc.h to new file mpi2_image.h Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
113 lines
4.4 KiB
C
113 lines
4.4 KiB
C
/*
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* Copyright 2000-2020 Broadcom Inc. All rights reserved.
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*
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*
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* Name: mpi2_pci.h
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* Title: MPI PCIe Attached Devices structures and definitions.
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* Creation Date: October 9, 2012
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*
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* mpi2_pci.h Version: 02.00.03
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*
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* NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
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* prefix are for use only on MPI v2.5 products, and must not be used
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* with MPI v2.0 products. Unless otherwise noted, names beginning with
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* MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
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*
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* Version History
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* ---------------
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*
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* Date Version Description
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* -------- -------- ------------------------------------------------------
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* 03-16-15 02.00.00 Initial version.
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* 02-17-16 02.00.01 Removed AHCI support.
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* Removed SOP support.
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* 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to
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* NVME Encapsulated Request.
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* 07-22-18 02.00.03 Updted flags field for NVME Encapsulated req
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* --------------------------------------------------------------------------
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*/
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#ifndef MPI2_PCI_H
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#define MPI2_PCI_H
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/*
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*Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event
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*data and PCIe Configuration pages.
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*/
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#define MPI26_PCIE_DEVINFO_DIRECT_ATTACH (0x00000010)
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#define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE (0x0000000F)
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#define MPI26_PCIE_DEVINFO_NO_DEVICE (0x00000000)
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#define MPI26_PCIE_DEVINFO_PCI_SWITCH (0x00000001)
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#define MPI26_PCIE_DEVINFO_NVME (0x00000003)
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/****************************************************************************
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* NVMe Encapsulated message
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****************************************************************************/
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/*NVME Encapsulated Request Message */
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typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST {
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U16 DevHandle; /*0x00 */
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U8 ChainOffset; /*0x02 */
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U8 Function; /*0x03 */
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U16 EncapsulatedCommandLength; /*0x04 */
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U8 Reserved1; /*0x06 */
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U8 MsgFlags; /*0x07 */
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U8 VP_ID; /*0x08 */
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U8 VF_ID; /*0x09 */
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U16 Reserved2; /*0x0A */
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U32 Reserved3; /*0x0C */
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U64 ErrorResponseBaseAddress; /*0x10 */
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U16 ErrorResponseAllocationLength; /*0x18 */
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U16 Flags; /*0x1A */
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U32 DataLength; /*0x1C */
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U8 NVMe_Command[4]; /*0x20 */
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} MPI26_NVME_ENCAPSULATED_REQUEST, *PTR_MPI26_NVME_ENCAPSULATED_REQUEST,
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Mpi26NVMeEncapsulatedRequest_t, *pMpi26NVMeEncapsulatedRequest_t;
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/*defines for the Flags field */
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#define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP (0x0020)
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/*Submission Queue Type*/
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#define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK (0x0010)
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#define MPI26_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
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#define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010)
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/*Error Response Address Space */
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#define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR (0x000C)
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#define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR_MASK (0x000C)
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#define MPI26_NVME_FLAGS_SYSTEM_RSP_ADDR (0x0000)
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#define MPI26_NVME_FLAGS_IOCCTL_RSP_ADDR (0x0008)
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/* Data Direction*/
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#define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003)
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#define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000)
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#define MPI26_NVME_FLAGS_WRITE (0x0001)
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#define MPI26_NVME_FLAGS_READ (0x0002)
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#define MPI26_NVME_FLAGS_BIDIRECTIONAL (0x0003)
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/*NVMe Encapuslated Reply Message */
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typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY {
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U16 DevHandle; /*0x00 */
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U8 MsgLength; /*0x02 */
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U8 Function; /*0x03 */
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U16 EncapsulatedCommandLength; /*0x04 */
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U8 Reserved1; /*0x06 */
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U8 MsgFlags; /*0x07 */
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U8 VP_ID; /*0x08 */
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U8 VF_ID; /*0x09 */
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U16 Reserved2; /*0x0A */
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U16 Reserved3; /*0x0C */
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U16 IOCStatus; /*0x0E */
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U32 IOCLogInfo; /*0x10 */
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U16 ErrorResponseCount; /*0x14 */
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U16 Reserved4; /*0x16 */
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} MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
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*PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
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Mpi26NVMeEncapsulatedErrorReply_t,
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*pMpi26NVMeEncapsulatedErrorReply_t;
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#endif
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