mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 08:07:10 +07:00
1f03bf06e4
Commit b9562545ef ("bcma: complete workaround for BCMA43224 and
BCM4313") introduced the wrong masks for setting the chip control
registers - the "mask" parameter is inverse.
It should be the mask of bits *not* changed, which is admittedly a bit
non-intuitive.
The incorrect mask not only causes the driver to not work correctly on
the chips affected (eg the BCM43224 on the Macbook Air 4,2) but the
state persists over a soft reset, causing the next boot to not
necessarily see the device correctly.
Reported-and-tested-by: Linus Torvalds <torvalds@linux-foundation.org>
Tested-by: Seth Forshee <seth.forshee@canonical.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Arend Van Spriel <arend@broadcom.com>
Cc: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Cc: Brett Rudley <brudley@broadcom.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
501 lines
15 KiB
C
501 lines
15 KiB
C
/*
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* Broadcom specific AMBA
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* ChipCommon Power Management Unit driver
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*
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* Copyright 2009, Michael Buesch <m@bues.ch>
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* Copyright 2007, 2011, Broadcom Corporation
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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}
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void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
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void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
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void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set)
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{
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
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bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
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void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
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bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
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static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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u32 min_msk = 0, max_msk = 0;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4313:
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min_msk = 0x200D;
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max_msk = 0xFFFF;
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break;
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default:
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bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
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bus->chipinfo.id);
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}
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/* Set the resource masks. */
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if (min_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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if (max_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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/* Add some delay; allow resources to come up and settle. */
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mdelay(2);
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}
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/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
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void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
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{
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struct bcma_bus *bus = cc->core->bus;
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u32 val;
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val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
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if (enable) {
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val |= BCMA_CHIPCTL_4331_EXTPA_EN;
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if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
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val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
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else if (bus->chipinfo.rev > 0)
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val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
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} else {
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val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
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val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
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val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
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}
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
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}
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void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4313:
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/* enable 12 mA drive strenth for 4313 and set chipControl
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register bit 1 */
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bcma_chipco_chipctl_maskset(cc, 0,
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~BCMA_CCTRL_4313_12MA_LED_DRIVE,
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BCMA_CCTRL_4313_12MA_LED_DRIVE);
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break;
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case BCMA_CHIP_ID_BCM4331:
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case BCMA_CHIP_ID_BCM43431:
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/* Ext PA lines must be enabled for tx on BCM4331 */
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bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
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break;
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case BCMA_CHIP_ID_BCM43224:
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case BCMA_CHIP_ID_BCM43421:
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/* enable 12 mA drive strenth for 43224 and set chipControl
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register bit 15 */
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if (bus->chipinfo.rev == 0) {
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bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
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~BCMA_CCTRL_43224_GPIO_TOGGLE,
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BCMA_CCTRL_43224_GPIO_TOGGLE);
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bcma_chipco_chipctl_maskset(cc, 0,
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~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
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BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
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} else {
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bcma_chipco_chipctl_maskset(cc, 0,
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~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
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BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
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}
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break;
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default:
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bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
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bus->chipinfo.id);
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}
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}
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void bcma_pmu_init(struct bcma_drv_cc *cc)
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{
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u32 pmucap;
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pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
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cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
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bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
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cc->pmu.rev, pmucap);
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if (cc->pmu.rev == 1)
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bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
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~BCMA_CC_PMU_CTL_NOILPONW);
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else
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bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
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BCMA_CC_PMU_CTL_NOILPONW);
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bcma_pmu_resources_init(cc);
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bcma_pmu_workarounds(cc);
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}
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u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4716:
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case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM47162:
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case BCMA_CHIP_ID_BCM4313:
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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case BCMA_CHIP_ID_BCM53572:
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/* always 20Mhz */
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return 20000 * 1000;
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case BCMA_CHIP_ID_BCM5356:
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case BCMA_CHIP_ID_BCM4706:
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/* always 25Mhz */
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return 25000 * 1000;
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default:
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bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
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}
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return BCMA_CC_PMU_ALP_CLOCK;
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}
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/* Find the output of the "m" pll divider given pll controls that start with
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* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
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*/
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static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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{
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u32 tmp, div, ndiv, p1, p2, fc;
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struct bcma_bus *bus = cc->core->bus;
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BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
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BUG_ON(!m || m > 4);
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
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/* Detect failure in clock setting */
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tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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if (tmp & 0x40000)
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return 133 * 1000000;
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}
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
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p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
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p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
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div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
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BCMA_CC_PPL_MDIV_MASK;
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
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ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
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/* Do calculation in Mhz */
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fc = bcma_pmu_alp_clock(cc) / 1000000;
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fc = (p1 * ndiv * fc) / p2;
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/* Return clock in Hertz */
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return (fc / div) * 1000000;
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}
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static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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{
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u32 tmp, ndiv, p1div, p2div;
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u32 clock;
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BUG_ON(!m || m > 4);
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/* Get N, P1 and P2 dividers to determine CPU clock */
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
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ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
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>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
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p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
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>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
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p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
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>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
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tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
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/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
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clock = (25000000 / 4) * ndiv * p2div / p1div;
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else
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/* Fixed reference clock 25MHz and m = 2 */
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clock = (25000000 / 2) * ndiv * p2div / p1div;
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if (m == BCMA_CC_PMU5_MAINPLL_SSB)
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clock = clock / 4;
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return clock;
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}
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/* query bus clock frequency for PMU-enabled chipcommon */
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u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4716:
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case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM47162:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM5356:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM53572:
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return 75000000;
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default:
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bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
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}
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return BCMA_CC_PMU_HT_CLOCK;
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}
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/* query cpu clock frequency for PMU-enabled chipcommon */
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u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
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return 300000000;
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if (cc->pmu.rev >= 5) {
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u32 pll;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock_bcm4706(cc,
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BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_CPU);
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case BCMA_CHIP_ID_BCM5356:
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pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
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break;
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
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break;
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default:
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pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
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break;
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}
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return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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}
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return bcma_pmu_get_clockcontrol(cc);
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}
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static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
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u32 value)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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}
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void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
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{
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u32 tmp = 0;
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u8 phypll_offset = 0;
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u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
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u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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case BCMA_CHIP_ID_BCM53572:
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/* 5357[ab]0, 43236[ab]0, and 6362b0 */
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/* BCM5357 needs to touch PLL1_PLLCTL[02],
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so offset PLL0_PLLCTL[02] by 6 */
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phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
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/* RMW only the P1 divider */
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
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tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
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tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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/* RMW only the int feedback divider */
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
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tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
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tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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tmp = 1 << 10;
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break;
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case BCMA_CHIP_ID_BCM4331:
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case BCMA_CHIP_ID_BCM43431:
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if (spuravoid == 2) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11500014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x0FC00a08);
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} else if (spuravoid == 1) {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11500014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x0F600a08);
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} else {
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
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0x11100014);
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000a08);
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}
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tmp = 1 << 10;
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break;
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|
case BCMA_CHIP_ID_BCM43224:
|
|
case BCMA_CHIP_ID_BCM43225:
|
|
case BCMA_CHIP_ID_BCM43421:
|
|
if (spuravoid == 1) {
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
|
|
0x11500010);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
|
|
0x000C0C06);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x0F600a08);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
|
|
0x00000000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
|
|
0x2001E920);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
} else {
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
|
|
0x11100010);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
|
|
0x000c0c06);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x03000a08);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
|
|
0x00000000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
|
|
0x200005c0);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
}
|
|
tmp = 1 << 10;
|
|
break;
|
|
|
|
case BCMA_CHIP_ID_BCM4716:
|
|
case BCMA_CHIP_ID_BCM4748:
|
|
case BCMA_CHIP_ID_BCM47162:
|
|
if (spuravoid == 1) {
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
|
|
0x11500060);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
|
|
0x080C0C06);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x0F600000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
|
|
0x00000000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
|
|
0x2001E924);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
} else {
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
|
|
0x11100060);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
|
|
0x080c0c06);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x03000000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
|
|
0x00000000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
|
|
0x200005c0);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
}
|
|
|
|
tmp = 3 << 9;
|
|
break;
|
|
|
|
case BCMA_CHIP_ID_BCM43227:
|
|
case BCMA_CHIP_ID_BCM43228:
|
|
case BCMA_CHIP_ID_BCM43428:
|
|
/* LCNXN */
|
|
/* PLL Settings for spur avoidance on/off mode,
|
|
no on2 support for 43228A0 */
|
|
if (spuravoid == 1) {
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
|
|
0x01100014);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
|
|
0x040C0C06);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x03140A08);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
|
|
0x00333333);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
|
|
0x202C2820);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
} else {
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
|
|
0x11100014);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
|
|
0x040c0c06);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
|
|
0x03000a08);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
|
|
0x00000000);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
|
|
0x200005c0);
|
|
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
|
|
0x88888815);
|
|
}
|
|
tmp = 1 << 10;
|
|
break;
|
|
default:
|
|
bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
|
|
bus->chipinfo.id);
|
|
break;
|
|
}
|
|
|
|
tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
|
|
bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
|
|
}
|
|
EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
|