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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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eb13cf8345
PCIe has a range property, so the unit name should contain an address. Make use of the label to enable individual PCIe busses. Also, fixup the synology dtsi file which added a label pcie2 rather than using the existing pcie1 label. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
110 lines
2.4 KiB
Plaintext
110 lines
2.4 KiB
Plaintext
/*
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* Marvell RD88F6192 Board descrition
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*
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions that are common between the three
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* variants of the Marvell Kirkwood Development Board.
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*/
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/dts-v1/;
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#include "kirkwood.dtsi"
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#include "kirkwood-6192.dtsi"
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/ {
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model = "Marvell RD88F6192 reference design";
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compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood";
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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stdout-path = &uart0;
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};
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ocp@f1000000 {
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pinctrl: pin-controller@10000 {
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pinctrl-0 = <&pmx_usb_power>;
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pinctrl-names = "default";
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pmx_usb_power: pmx-usb-power {
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marvell,pins = "mpp10";
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marvell,function = "gpo";
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};
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};
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serial@12000 {
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status = "okay";
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};
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spi@10600 {
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status = "okay";
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m25p128@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <20000000>;
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mode = <0>;
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};
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};
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sata@80000 {
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status = "okay";
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nr-ports = <2>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&pmx_usb_power>;
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pinctrl-names = "default";
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usb_power: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "USB VBUS";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&mdio {
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status = "okay";
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ethphy0: ethernet-phy@8 {
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reg = <8>;
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};
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};
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ð0 {
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status = "okay";
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ethernet0-port@0 {
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phy-handle = <ðphy0>;
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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};
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