Arun Siluvery a786d53a2c drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist ... Required for WaDisableLSQCROPERFforOCL:bxt According to WA database these are only applicable for BXT:A0 but since A0 and A1 shares the same GT these are extended for A1 as well. This register is added to HW whitelist to support WA required for future enabling of pre-emptive command execution, WA implementation will be in userspace and it cannot program this register if it is not on HW whitelist. v2: explain purpose of changes (Chris) Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-6-git-send-email-arun.siluvery@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2016-01-25 16:48:35 +01:00
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drm	drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist	2016-01-25 16:48:35 +01:00
host1x	gpu: host1x: Add Tegra210 support	2015-12-14 10:50:33 +01:00
ipu-v3	gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports	2015-11-24 11:30:17 +01:00
vga	Merge tag 'topic/drm-misc-2016-01-17' of git://anongit.freedesktop.org/drm-intel into drm-next	2016-01-18 07:01:16 +10:00
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