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8f1be5bd14
Exynos LPASS requires some clocks to be enabled to make any access to its registers. This patch adds code for handling such clocks. For current set of registers it is enough to keep sfr0_ctrl clock enabled. Till now it worked only because those clocks were enabled by bootloader and driver probe() happened before they were disabled by clock core because of lack of users. Handling those clocks is also needed to make it possible to enable support for audio power domain. This patch requires adding sfr0_ctrl clock to device tree. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
75 lines
2.0 KiB
Plaintext
75 lines
2.0 KiB
Plaintext
Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
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Required properties:
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- compatible : "samsung,exynos5433-lpass"
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- reg : should contain the LPASS top SFR region location
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and size
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- clock-names : should contain following required clocks: "sfr0_ctrl"
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- clocks : should contain clock specifiers of all clocks, which
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input names have been specified in clock-names
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property, in same order.
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- #address-cells : should be 1
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- #size-cells : should be 1
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- ranges : must be present
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Each IP block of the Low Power Audio Subsystem should be specified as
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an optional sub-node. For "samsung,exynos5433-lpass" compatible this includes:
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UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
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Bindings of the sub-nodes are described in:
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../serial/samsung_uart.txt
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../sound/samsung-i2s.txt
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../dma/arm-pl330.txt
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Example:
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audio-subsystem {
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compatible = "samsung,exynos5433-lpass";
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reg = <0x11400000 0x100>, <0x11500000 0x08>;
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clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
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clock-names = "sfr0_ctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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adma: adma@11420000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11420000 0x1000>;
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interrupts = <0 73 0>;
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clocks = <&cmu_aud CLK_ACLK_DMAC>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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i2s0: i2s0@11440000 {
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compatible = "samsung,exynos7-i2s";
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reg = <0x11440000 0x100>;
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dmas = <&adma 0 &adma 2>;
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dma-names = "tx", "rx";
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interrupts = <0 70 0>;
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clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
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<&cmu_aud CLK_SCLK_AUD_I2S>,
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<&cmu_aud CLK_SCLK_I2S_BCLK>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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status = "disabled";
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};
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serial_3: serial@11460000 {
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compatible = "samsung,exynos5433-uart";
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reg = <0x11460000 0x100>;
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interrupts = <0 67 0>;
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clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
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<&cmu_aud CLK_SCLK_AUD_UART>;
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clock-names = "uart", "clk_uart_baud0";
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pinctrl-names = "default";
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pinctrl-0 = <&uart_aud_bus>;
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status = "disabled";
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};
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};
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