Stephane Viau a73f3382da drm/msm/mdp5: only flush on a CRTC ->atomic_flush() ... MDP5 hardware has some limitation and requires to avoid flushing registers more than once between two Vblanks. This change removes all FLUSH operations (except for HW cursor) beside the one coming from a CRTC's ->atomic_flush(). This avoid this type of behavior (eg: CRTC + 1 plane overlay): [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_ctl_commit] flush (20040) CTL + LM0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank and replaces it by: [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank Only *one* FLUSH is called between Vblanks interrupts. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2015-04-01 19:29:33 -04:00
..
drm	drm/msm/mdp5: only flush on a CRTC ->atomic_flush()	2015-04-01 19:29:33 -04:00
host1x	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00
ipu-v3	gpu: ipu-v3: do not divide by zero if the pixel clock is too large	2015-02-23 17:18:59 +01:00
vga
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00