mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 23:33:22 +07:00
192f0f8e9d
Notable changes: - Removal of the NPU DMA code, used by the out-of-tree Nvidia driver, as well as some other functions only used by drivers that haven't (yet?) made it upstream. - A fix for a bug in our handling of hardware watchpoints (eg. perf record -e mem: ...) which could lead to register corruption and kernel crashes. - Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for vmalloc when using the Radix MMU. - A large but incremental rewrite of our exception handling code to use gas macros rather than multiple levels of nested CPP macros. And the usual small fixes, cleanups and improvements. Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab, Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann, Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz, Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj Jitindar Singh, Thiago Jung Bauermann, YueHaibing. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdKVoLAAoJEFHr6jzI4aWA0kIP/A6shIbbE7H5W2hFrqt/PPPK 3+VrvPKbOFF+W6hcE/RgSZmEnUo0svdNjHUd/eMfFS1vb/uRt2QDdrsHUNNwURQL M2mcLXFwYpnjSjb/XMgDbHpAQxjeGfTdYLonUIejN7Rk8KQUeLyKQ3SBn6kfMc46 DnUUcPcjuRGaETUmVuZZ4e40ZWbJp8PKDrSJOuUrTPXMaK5ciNbZk5mCWXGbYl6G BMQAyv4ld/417rNTjBEP/T2foMJtioAt4W6mtlgdkOTdIEZnFU67nNxDBthNSu2c 95+I+/sML4KOp1R4yhqLSLIDDbc3bg3c99hLGij0d948z3bkSZ8bwnPaUuy70C4v U8rvl/+N6C6H3DgSsPE/Gnkd8DnudqWY8nULc+8p3fXljGwww6/Qgt+6yCUn8BdW WgixkSjKgjDmzTw8trIUNEqORrTVle7cM2hIyIK2Q5T4kWzNQxrLZ/x/3wgoYjUa 1KwIzaRo5JKZ9D3pJnJ5U+knE2/90rJIyfcp0W6ygyJsWKi2GNmq1eN3sKOw0IxH Tg86RENIA/rEMErNOfP45sLteMuTR7of7peCG3yumIOZqsDVYAzerpvtSgip2cvK aG+9HcYlBFOOOF9Dabi8GXsTBLXLfwiyjjLSpA9eXPwW8KObgiNfTZa7ujjTPvis 4mk9oukFTFUpfhsMmI3T =3dBZ -----END PGP SIGNATURE----- Merge tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: "Notable changes: - Removal of the NPU DMA code, used by the out-of-tree Nvidia driver, as well as some other functions only used by drivers that haven't (yet?) made it upstream. - A fix for a bug in our handling of hardware watchpoints (eg. perf record -e mem: ...) which could lead to register corruption and kernel crashes. - Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for vmalloc when using the Radix MMU. - A large but incremental rewrite of our exception handling code to use gas macros rather than multiple levels of nested CPP macros. And the usual small fixes, cleanups and improvements. Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab, Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann, Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz, Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj Jitindar Singh, Thiago Jung Bauermann, YueHaibing" * tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (163 commits) powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state. powerpc/eeh: Handle hugepages in ioremap space ocxl: Update for AFU descriptor template version 1.1 powerpc/boot: pass CONFIG options in a simpler and more robust way powerpc/boot: add {get, put}_unaligned_be32 to xz_config.h powerpc/irq: Don't WARN continuously in arch_local_irq_restore() powerpc/module64: Use symbolic instructions names. powerpc/module32: Use symbolic instructions names. powerpc: Move PPC_HA() PPC_HI() and PPC_LO() to ppc-opcode.h powerpc/module64: Fix comment in R_PPC64_ENTRY handling powerpc/boot: Add lzo support for uImage powerpc/boot: Add lzma support for uImage powerpc/boot: don't force gzipped uImage powerpc/8xx: Add microcode patch to move SMC parameter RAM. powerpc/8xx: Use IO accessors in microcode programming. powerpc/8xx: replace #ifdefs by IS_ENABLED() in microcode.c powerpc/8xx: refactor programming of microcode CPM params. powerpc/8xx: refactor printing of microcode patch name. powerpc/8xx: Refactor microcode write powerpc/8xx: refactor writing of CPM microcode arrays ...
680 lines
16 KiB
C
680 lines
16 KiB
C
/*
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* PPC Huge TLB Page Support for Kernel.
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*
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* Copyright (C) 2003 David Gibson, IBM Corporation.
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* Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
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*
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* Based on the IA-32 version:
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* Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
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*/
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/hugetlb.h>
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#include <linux/export.h>
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#include <linux/of_fdt.h>
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#include <linux/memblock.h>
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#include <linux/moduleparam.h>
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#include <linux/swap.h>
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#include <linux/swapops.h>
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#include <linux/kmemleak.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/tlb.h>
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#include <asm/setup.h>
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#include <asm/hugetlb.h>
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#include <asm/pte-walk.h>
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bool hugetlb_disabled = false;
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#define hugepd_none(hpd) (hpd_val(hpd) == 0)
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#define PTE_T_ORDER (__builtin_ffs(sizeof(pte_t)) - __builtin_ffs(sizeof(void *)))
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pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr, unsigned long sz)
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{
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/*
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* Only called for hugetlbfs pages, hence can ignore THP and the
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* irq disabled walk.
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*/
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return __find_linux_pte(mm->pgd, addr, NULL, NULL);
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}
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static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
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unsigned long address, unsigned int pdshift,
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unsigned int pshift, spinlock_t *ptl)
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{
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struct kmem_cache *cachep;
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pte_t *new;
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int i;
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int num_hugepd;
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if (pshift >= pdshift) {
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cachep = PGT_CACHE(PTE_T_ORDER);
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num_hugepd = 1 << (pshift - pdshift);
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} else if (IS_ENABLED(CONFIG_PPC_8xx)) {
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cachep = PGT_CACHE(PTE_INDEX_SIZE);
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num_hugepd = 1;
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} else {
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cachep = PGT_CACHE(pdshift - pshift);
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num_hugepd = 1;
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}
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if (!cachep) {
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WARN_ONCE(1, "No page table cache created for hugetlb tables");
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return -ENOMEM;
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}
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new = kmem_cache_alloc(cachep, pgtable_gfp_flags(mm, GFP_KERNEL));
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BUG_ON(pshift > HUGEPD_SHIFT_MASK);
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BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
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if (!new)
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return -ENOMEM;
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/*
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* Make sure other cpus find the hugepd set only after a
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* properly initialized page table is visible to them.
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* For more details look for comment in __pte_alloc().
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*/
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smp_wmb();
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spin_lock(ptl);
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/*
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* We have multiple higher-level entries that point to the same
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* actual pte location. Fill in each as we go and backtrack on error.
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* We need all of these so the DTLB pgtable walk code can find the
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* right higher-level entry without knowing if it's a hugepage or not.
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*/
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for (i = 0; i < num_hugepd; i++, hpdp++) {
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if (unlikely(!hugepd_none(*hpdp)))
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break;
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hugepd_populate(hpdp, new, pshift);
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}
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/* If we bailed from the for loop early, an error occurred, clean up */
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if (i < num_hugepd) {
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for (i = i - 1 ; i >= 0; i--, hpdp--)
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*hpdp = __hugepd(0);
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kmem_cache_free(cachep, new);
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} else {
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kmemleak_ignore(new);
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}
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spin_unlock(ptl);
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return 0;
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}
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/*
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* At this point we do the placement change only for BOOK3S 64. This would
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* possibly work on other subarchs.
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*/
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pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
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{
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pgd_t *pg;
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pud_t *pu;
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pmd_t *pm;
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hugepd_t *hpdp = NULL;
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unsigned pshift = __ffs(sz);
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unsigned pdshift = PGDIR_SHIFT;
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spinlock_t *ptl;
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addr &= ~(sz-1);
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pg = pgd_offset(mm, addr);
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#ifdef CONFIG_PPC_BOOK3S_64
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if (pshift == PGDIR_SHIFT)
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/* 16GB huge page */
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return (pte_t *) pg;
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else if (pshift > PUD_SHIFT) {
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/*
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* We need to use hugepd table
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*/
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ptl = &mm->page_table_lock;
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hpdp = (hugepd_t *)pg;
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} else {
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pdshift = PUD_SHIFT;
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pu = pud_alloc(mm, pg, addr);
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if (!pu)
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return NULL;
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if (pshift == PUD_SHIFT)
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return (pte_t *)pu;
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else if (pshift > PMD_SHIFT) {
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ptl = pud_lockptr(mm, pu);
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hpdp = (hugepd_t *)pu;
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} else {
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pdshift = PMD_SHIFT;
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pm = pmd_alloc(mm, pu, addr);
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if (!pm)
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return NULL;
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if (pshift == PMD_SHIFT)
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/* 16MB hugepage */
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return (pte_t *)pm;
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else {
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ptl = pmd_lockptr(mm, pm);
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hpdp = (hugepd_t *)pm;
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}
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}
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}
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#else
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if (pshift >= PGDIR_SHIFT) {
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ptl = &mm->page_table_lock;
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hpdp = (hugepd_t *)pg;
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} else {
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pdshift = PUD_SHIFT;
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pu = pud_alloc(mm, pg, addr);
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if (!pu)
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return NULL;
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if (pshift >= PUD_SHIFT) {
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ptl = pud_lockptr(mm, pu);
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hpdp = (hugepd_t *)pu;
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} else {
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pdshift = PMD_SHIFT;
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pm = pmd_alloc(mm, pu, addr);
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if (!pm)
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return NULL;
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ptl = pmd_lockptr(mm, pm);
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hpdp = (hugepd_t *)pm;
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}
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}
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#endif
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if (!hpdp)
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return NULL;
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BUG_ON(!hugepd_none(*hpdp) && !hugepd_ok(*hpdp));
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if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr,
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pdshift, pshift, ptl))
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return NULL;
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return hugepte_offset(*hpdp, addr, pdshift);
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}
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* Tracks gpages after the device tree is scanned and before the
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* huge_boot_pages list is ready on pseries.
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*/
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#define MAX_NUMBER_GPAGES 1024
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__initdata static u64 gpage_freearray[MAX_NUMBER_GPAGES];
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__initdata static unsigned nr_gpages;
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/*
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* Build list of addresses of gigantic pages. This function is used in early
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* boot before the buddy allocator is setup.
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*/
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void __init pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages)
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{
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if (!addr)
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return;
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while (number_of_pages > 0) {
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gpage_freearray[nr_gpages] = addr;
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nr_gpages++;
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number_of_pages--;
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addr += page_size;
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}
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}
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int __init pseries_alloc_bootmem_huge_page(struct hstate *hstate)
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{
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struct huge_bootmem_page *m;
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if (nr_gpages == 0)
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return 0;
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m = phys_to_virt(gpage_freearray[--nr_gpages]);
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gpage_freearray[nr_gpages] = 0;
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list_add(&m->list, &huge_boot_pages);
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m->hstate = hstate;
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return 1;
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}
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#endif
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int __init alloc_bootmem_huge_page(struct hstate *h)
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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if (firmware_has_feature(FW_FEATURE_LPAR) && !radix_enabled())
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return pseries_alloc_bootmem_huge_page(h);
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#endif
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return __alloc_bootmem_huge_page(h);
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}
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#ifndef CONFIG_PPC_BOOK3S_64
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#define HUGEPD_FREELIST_SIZE \
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((PAGE_SIZE - sizeof(struct hugepd_freelist)) / sizeof(pte_t))
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struct hugepd_freelist {
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struct rcu_head rcu;
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unsigned int index;
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void *ptes[0];
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};
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static DEFINE_PER_CPU(struct hugepd_freelist *, hugepd_freelist_cur);
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static void hugepd_free_rcu_callback(struct rcu_head *head)
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{
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struct hugepd_freelist *batch =
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container_of(head, struct hugepd_freelist, rcu);
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unsigned int i;
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for (i = 0; i < batch->index; i++)
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kmem_cache_free(PGT_CACHE(PTE_T_ORDER), batch->ptes[i]);
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free_page((unsigned long)batch);
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}
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static void hugepd_free(struct mmu_gather *tlb, void *hugepte)
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{
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struct hugepd_freelist **batchp;
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batchp = &get_cpu_var(hugepd_freelist_cur);
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if (atomic_read(&tlb->mm->mm_users) < 2 ||
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mm_is_thread_local(tlb->mm)) {
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kmem_cache_free(PGT_CACHE(PTE_T_ORDER), hugepte);
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put_cpu_var(hugepd_freelist_cur);
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return;
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}
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if (*batchp == NULL) {
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*batchp = (struct hugepd_freelist *)__get_free_page(GFP_ATOMIC);
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(*batchp)->index = 0;
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}
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(*batchp)->ptes[(*batchp)->index++] = hugepte;
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if ((*batchp)->index == HUGEPD_FREELIST_SIZE) {
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call_rcu(&(*batchp)->rcu, hugepd_free_rcu_callback);
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*batchp = NULL;
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}
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put_cpu_var(hugepd_freelist_cur);
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}
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#else
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static inline void hugepd_free(struct mmu_gather *tlb, void *hugepte) {}
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#endif
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static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshift,
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unsigned long start, unsigned long end,
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unsigned long floor, unsigned long ceiling)
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{
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pte_t *hugepte = hugepd_page(*hpdp);
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int i;
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unsigned long pdmask = ~((1UL << pdshift) - 1);
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unsigned int num_hugepd = 1;
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unsigned int shift = hugepd_shift(*hpdp);
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/* Note: On fsl the hpdp may be the first of several */
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if (shift > pdshift)
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num_hugepd = 1 << (shift - pdshift);
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start &= pdmask;
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if (start < floor)
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return;
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if (ceiling) {
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ceiling &= pdmask;
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if (! ceiling)
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return;
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}
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if (end - 1 > ceiling - 1)
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return;
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for (i = 0; i < num_hugepd; i++, hpdp++)
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*hpdp = __hugepd(0);
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if (shift >= pdshift)
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hugepd_free(tlb, hugepte);
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else if (IS_ENABLED(CONFIG_PPC_8xx))
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pgtable_free_tlb(tlb, hugepte,
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get_hugepd_cache_index(PTE_INDEX_SIZE));
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else
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pgtable_free_tlb(tlb, hugepte,
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get_hugepd_cache_index(pdshift - shift));
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}
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static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
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unsigned long addr, unsigned long end,
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unsigned long floor, unsigned long ceiling)
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{
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pmd_t *pmd;
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unsigned long next;
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unsigned long start;
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start = addr;
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do {
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unsigned long more;
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pmd = pmd_offset(pud, addr);
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next = pmd_addr_end(addr, end);
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if (!is_hugepd(__hugepd(pmd_val(*pmd)))) {
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/*
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* if it is not hugepd pointer, we should already find
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* it cleared.
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*/
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WARN_ON(!pmd_none_or_clear_bad(pmd));
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continue;
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}
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/*
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* Increment next by the size of the huge mapping since
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* there may be more than one entry at this level for a
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* single hugepage, but all of them point to
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* the same kmem cache that holds the hugepte.
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*/
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more = addr + (1 << hugepd_shift(*(hugepd_t *)pmd));
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if (more > next)
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next = more;
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free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT,
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addr, next, floor, ceiling);
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} while (addr = next, addr != end);
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start &= PUD_MASK;
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if (start < floor)
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return;
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if (ceiling) {
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ceiling &= PUD_MASK;
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if (!ceiling)
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return;
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}
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if (end - 1 > ceiling - 1)
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return;
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pmd = pmd_offset(pud, start);
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pud_clear(pud);
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pmd_free_tlb(tlb, pmd, start);
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mm_dec_nr_pmds(tlb->mm);
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}
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static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
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unsigned long addr, unsigned long end,
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unsigned long floor, unsigned long ceiling)
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{
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pud_t *pud;
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unsigned long next;
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unsigned long start;
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start = addr;
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do {
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pud = pud_offset(pgd, addr);
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|
next = pud_addr_end(addr, end);
|
|
if (!is_hugepd(__hugepd(pud_val(*pud)))) {
|
|
if (pud_none_or_clear_bad(pud))
|
|
continue;
|
|
hugetlb_free_pmd_range(tlb, pud, addr, next, floor,
|
|
ceiling);
|
|
} else {
|
|
unsigned long more;
|
|
/*
|
|
* Increment next by the size of the huge mapping since
|
|
* there may be more than one entry at this level for a
|
|
* single hugepage, but all of them point to
|
|
* the same kmem cache that holds the hugepte.
|
|
*/
|
|
more = addr + (1 << hugepd_shift(*(hugepd_t *)pud));
|
|
if (more > next)
|
|
next = more;
|
|
|
|
free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT,
|
|
addr, next, floor, ceiling);
|
|
}
|
|
} while (addr = next, addr != end);
|
|
|
|
start &= PGDIR_MASK;
|
|
if (start < floor)
|
|
return;
|
|
if (ceiling) {
|
|
ceiling &= PGDIR_MASK;
|
|
if (!ceiling)
|
|
return;
|
|
}
|
|
if (end - 1 > ceiling - 1)
|
|
return;
|
|
|
|
pud = pud_offset(pgd, start);
|
|
pgd_clear(pgd);
|
|
pud_free_tlb(tlb, pud, start);
|
|
mm_dec_nr_puds(tlb->mm);
|
|
}
|
|
|
|
/*
|
|
* This function frees user-level page tables of a process.
|
|
*/
|
|
void hugetlb_free_pgd_range(struct mmu_gather *tlb,
|
|
unsigned long addr, unsigned long end,
|
|
unsigned long floor, unsigned long ceiling)
|
|
{
|
|
pgd_t *pgd;
|
|
unsigned long next;
|
|
|
|
/*
|
|
* Because there are a number of different possible pagetable
|
|
* layouts for hugepage ranges, we limit knowledge of how
|
|
* things should be laid out to the allocation path
|
|
* (huge_pte_alloc(), above). Everything else works out the
|
|
* structure as it goes from information in the hugepd
|
|
* pointers. That means that we can't here use the
|
|
* optimization used in the normal page free_pgd_range(), of
|
|
* checking whether we're actually covering a large enough
|
|
* range to have to do anything at the top level of the walk
|
|
* instead of at the bottom.
|
|
*
|
|
* To make sense of this, you should probably go read the big
|
|
* block comment at the top of the normal free_pgd_range(),
|
|
* too.
|
|
*/
|
|
|
|
do {
|
|
next = pgd_addr_end(addr, end);
|
|
pgd = pgd_offset(tlb->mm, addr);
|
|
if (!is_hugepd(__hugepd(pgd_val(*pgd)))) {
|
|
if (pgd_none_or_clear_bad(pgd))
|
|
continue;
|
|
hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling);
|
|
} else {
|
|
unsigned long more;
|
|
/*
|
|
* Increment next by the size of the huge mapping since
|
|
* there may be more than one entry at the pgd level
|
|
* for a single hugepage, but all of them point to the
|
|
* same kmem cache that holds the hugepte.
|
|
*/
|
|
more = addr + (1 << hugepd_shift(*(hugepd_t *)pgd));
|
|
if (more > next)
|
|
next = more;
|
|
|
|
free_hugepd_range(tlb, (hugepd_t *)pgd, PGDIR_SHIFT,
|
|
addr, next, floor, ceiling);
|
|
}
|
|
} while (addr = next, addr != end);
|
|
}
|
|
|
|
struct page *follow_huge_pd(struct vm_area_struct *vma,
|
|
unsigned long address, hugepd_t hpd,
|
|
int flags, int pdshift)
|
|
{
|
|
pte_t *ptep;
|
|
spinlock_t *ptl;
|
|
struct page *page = NULL;
|
|
unsigned long mask;
|
|
int shift = hugepd_shift(hpd);
|
|
struct mm_struct *mm = vma->vm_mm;
|
|
|
|
retry:
|
|
/*
|
|
* hugepage directory entries are protected by mm->page_table_lock
|
|
* Use this instead of huge_pte_lockptr
|
|
*/
|
|
ptl = &mm->page_table_lock;
|
|
spin_lock(ptl);
|
|
|
|
ptep = hugepte_offset(hpd, address, pdshift);
|
|
if (pte_present(*ptep)) {
|
|
mask = (1UL << shift) - 1;
|
|
page = pte_page(*ptep);
|
|
page += ((address & mask) >> PAGE_SHIFT);
|
|
if (flags & FOLL_GET)
|
|
get_page(page);
|
|
} else {
|
|
if (is_hugetlb_entry_migration(*ptep)) {
|
|
spin_unlock(ptl);
|
|
__migration_entry_wait(mm, ptep, ptl);
|
|
goto retry;
|
|
}
|
|
}
|
|
spin_unlock(ptl);
|
|
return page;
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_MM_SLICES
|
|
unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
|
|
unsigned long len, unsigned long pgoff,
|
|
unsigned long flags)
|
|
{
|
|
struct hstate *hstate = hstate_file(file);
|
|
int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
|
|
|
|
#ifdef CONFIG_PPC_RADIX_MMU
|
|
if (radix_enabled())
|
|
return radix__hugetlb_get_unmapped_area(file, addr, len,
|
|
pgoff, flags);
|
|
#endif
|
|
return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1);
|
|
}
|
|
#endif
|
|
|
|
unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
|
|
{
|
|
/* With radix we don't use slice, so derive it from vma*/
|
|
if (IS_ENABLED(CONFIG_PPC_MM_SLICES) && !radix_enabled()) {
|
|
unsigned int psize = get_slice_psize(vma->vm_mm, vma->vm_start);
|
|
|
|
return 1UL << mmu_psize_to_shift(psize);
|
|
}
|
|
return vma_kernel_pagesize(vma);
|
|
}
|
|
|
|
static int __init add_huge_page_size(unsigned long long size)
|
|
{
|
|
int shift = __ffs(size);
|
|
int mmu_psize;
|
|
|
|
/* Check that it is a page size supported by the hardware and
|
|
* that it fits within pagetable and slice limits. */
|
|
if (size <= PAGE_SIZE || !is_power_of_2(size))
|
|
return -EINVAL;
|
|
|
|
mmu_psize = check_and_get_huge_psize(shift);
|
|
if (mmu_psize < 0)
|
|
return -EINVAL;
|
|
|
|
BUG_ON(mmu_psize_defs[mmu_psize].shift != shift);
|
|
|
|
/* Return if huge page size has already been setup */
|
|
if (size_to_hstate(size))
|
|
return 0;
|
|
|
|
hugetlb_add_hstate(shift - PAGE_SHIFT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init hugepage_setup_sz(char *str)
|
|
{
|
|
unsigned long long size;
|
|
|
|
size = memparse(str, &str);
|
|
|
|
if (add_huge_page_size(size) != 0) {
|
|
hugetlb_bad_size();
|
|
pr_err("Invalid huge page size specified(%llu)\n", size);
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
__setup("hugepagesz=", hugepage_setup_sz);
|
|
|
|
static int __init hugetlbpage_init(void)
|
|
{
|
|
bool configured = false;
|
|
int psize;
|
|
|
|
if (hugetlb_disabled) {
|
|
pr_info("HugeTLB support is disabled!\n");
|
|
return 0;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled() &&
|
|
!mmu_has_feature(MMU_FTR_16M_PAGE))
|
|
return -ENODEV;
|
|
|
|
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
|
|
unsigned shift;
|
|
unsigned pdshift;
|
|
|
|
if (!mmu_psize_defs[psize].shift)
|
|
continue;
|
|
|
|
shift = mmu_psize_to_shift(psize);
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
if (shift > PGDIR_SHIFT)
|
|
continue;
|
|
else if (shift > PUD_SHIFT)
|
|
pdshift = PGDIR_SHIFT;
|
|
else if (shift > PMD_SHIFT)
|
|
pdshift = PUD_SHIFT;
|
|
else
|
|
pdshift = PMD_SHIFT;
|
|
#else
|
|
if (shift < PUD_SHIFT)
|
|
pdshift = PMD_SHIFT;
|
|
else if (shift < PGDIR_SHIFT)
|
|
pdshift = PUD_SHIFT;
|
|
else
|
|
pdshift = PGDIR_SHIFT;
|
|
#endif
|
|
|
|
if (add_huge_page_size(1ULL << shift) < 0)
|
|
continue;
|
|
/*
|
|
* if we have pdshift and shift value same, we don't
|
|
* use pgt cache for hugepd.
|
|
*/
|
|
if (pdshift > shift && IS_ENABLED(CONFIG_PPC_8xx))
|
|
pgtable_cache_add(PTE_INDEX_SIZE);
|
|
else if (pdshift > shift)
|
|
pgtable_cache_add(pdshift - shift);
|
|
else if (IS_ENABLED(CONFIG_PPC_FSL_BOOK3E) || IS_ENABLED(CONFIG_PPC_8xx))
|
|
pgtable_cache_add(PTE_T_ORDER);
|
|
|
|
configured = true;
|
|
}
|
|
|
|
if (configured) {
|
|
if (IS_ENABLED(CONFIG_HUGETLB_PAGE_SIZE_VARIABLE))
|
|
hugetlbpage_init_default();
|
|
} else
|
|
pr_info("Failed to initialize. Disabling HugeTLB");
|
|
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(hugetlbpage_init);
|
|
|
|
void flush_dcache_icache_hugepage(struct page *page)
|
|
{
|
|
int i;
|
|
void *start;
|
|
|
|
BUG_ON(!PageCompound(page));
|
|
|
|
for (i = 0; i < (1UL << compound_order(page)); i++) {
|
|
if (!PageHighMem(page)) {
|
|
__flush_dcache_icache(page_address(page+i));
|
|
} else {
|
|
start = kmap_atomic(page+i);
|
|
__flush_dcache_icache(start);
|
|
kunmap_atomic(start);
|
|
}
|
|
}
|
|
}
|