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a69ba6293d
linux_dsm_epyc7002/arch/mips/include/asm/netlogic
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Jayachandran C a69ba6293d MIPS: Netlogic: Split XLP L1 i-cache among threads 
Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:20 +01:00
..
xlp-hal MIPS: Netlogic: Split XLP L1 i-cache among threads 2013-02-17 00:15:20 +01:00
xlr MIPS: Netlogic: Support for XLR/XLS Fast Message Network 2012-11-09 11:37:20 +01:00
common.h MIPS: Netlogic: Support for XLR/XLS Fast Message Network 2012-11-09 11:37:20 +01:00
haldefs.h MIPS: Netlogic: Add XLP platform files for XLP SoC 2011-12-07 22:04:56 +00:00
interrupt.h MIPS: Netlogic: Support for XLR/XLS Fast Message Network 2012-11-09 11:37:20 +01:00
mips-extns.h MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bit 2013-02-17 00:15:19 +01:00
psb-bootinfo.h MIPS: Platform files for XLR/XLS processor support 2011-05-19 09:55:40 +01:00