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766d45cbee
On PPC8xx, flushing instruction cache is performed by writing in register SPRN_IC_CST. This registers suffers CPU6 ERRATA. The patch rewrites the fonction in C so that CPU6 ERRATA will be handled transparently Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
/*
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* This file contains the routines for initializing the MMU
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* on the 8xx series of chips.
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* -- christophe
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*
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* Derived from arch/powerpc/mm/40x_mmu.c:
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/memblock.h>
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#include "mmu_decl.h"
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extern int __map_without_ltlbs;
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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/* Nothing to do for the time being but keep it similar to other PPC */
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}
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#define LARGE_PAGE_SIZE_4M (1<<22)
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#define LARGE_PAGE_SIZE_8M (1<<23)
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#define LARGE_PAGE_SIZE_64M (1<<26)
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unsigned long __init mmu_mapin_ram(unsigned long top)
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{
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unsigned long v, s, mapped;
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phys_addr_t p;
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v = KERNELBASE;
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p = 0;
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s = top;
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if (__map_without_ltlbs)
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return 0;
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#ifdef CONFIG_PPC_4K_PAGES
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while (s >= LARGE_PAGE_SIZE_8M) {
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pmd_t *pmdp;
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unsigned long val = p | MD_PS8MEG;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
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*pmdp++ = __pmd(val);
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*pmdp++ = __pmd(val + LARGE_PAGE_SIZE_4M);
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v += LARGE_PAGE_SIZE_8M;
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p += LARGE_PAGE_SIZE_8M;
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s -= LARGE_PAGE_SIZE_8M;
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}
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#else /* CONFIG_PPC_16K_PAGES */
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while (s >= LARGE_PAGE_SIZE_64M) {
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pmd_t *pmdp;
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unsigned long val = p | MD_PS8MEG;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
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*pmdp++ = __pmd(val);
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v += LARGE_PAGE_SIZE_64M;
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p += LARGE_PAGE_SIZE_64M;
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s -= LARGE_PAGE_SIZE_64M;
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}
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#endif
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mapped = top - s;
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/* If the size of RAM is not an exact power of two, we may not
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* have covered RAM in its entirety with 8 MiB
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* pages. Consequently, restrict the top end of RAM currently
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* allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
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* coverage with normal-sized pages (or other reasons) do not
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* attempt to allocate outside the allowed range.
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*/
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memblock_set_current_limit(mapped);
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return mapped;
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}
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void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/* We don't currently support the first MEMBLOCK not mapping 0
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* physical on those processors
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*/
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BUG_ON(first_memblock_base != 0);
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#ifdef CONFIG_PIN_TLB
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/* 8xx can only access 24MB at the moment */
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memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
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#else
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/* 8xx can only access 8MB at the moment */
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memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
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#endif
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}
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/*
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* Set up to use a given MMU context.
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* id is context number, pgd is PGD pointer.
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*
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* We place the physical address of the new task page directory loaded
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* into the MMU base register, and set the ASID compare register with
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* the new "context."
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*/
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void set_context(unsigned long id, pgd_t *pgd)
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{
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s16 offset = (s16)(__pa(swapper_pg_dir));
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#ifdef CONFIG_BDI_SWITCH
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pgd_t **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
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/* Context switch the PTE pointer for the Abatron BDI2000.
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* The PGDIR is passed as second argument.
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*/
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*(ptr + 1) = pgd;
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#endif
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/* Register M_TW will contain base address of level 1 table minus the
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* lower part of the kernel PGDIR base address, so that all accesses to
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* level 1 table are done relative to lower part of kernel PGDIR base
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* address.
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*/
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mtspr(SPRN_M_TW, __pa(pgd) - offset);
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/* Update context */
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mtspr(SPRN_M_CASID, id);
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/* sync */
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mb();
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}
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void flush_instruction_cache(void)
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{
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isync();
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mtspr(SPRN_IC_CST, IDC_INVALL);
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isync();
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}
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