mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 01:41:30 +07:00
80529ae5c1
Add hardware API for the exynos4x12 on s5p-jpeg. Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
378 lines
12 KiB
C
378 lines
12 KiB
C
/* linux/drivers/media/platform/s5p-jpeg/jpeg-regs.h
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*
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* Register definition file for Samsung JPEG codec driver
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*
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* Copyright (c) 2011-2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
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* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef JPEG_REGS_H_
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#define JPEG_REGS_H_
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/* Register and bit definitions for S5PC210 */
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/* JPEG mode register */
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#define S5P_JPGMOD 0x00
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#define S5P_PROC_MODE_MASK (0x1 << 3)
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#define S5P_PROC_MODE_DECOMPR (0x1 << 3)
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#define S5P_PROC_MODE_COMPR (0x0 << 3)
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#define S5P_SUBSAMPLING_MODE_MASK 0x7
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#define S5P_SUBSAMPLING_MODE_444 (0x0 << 0)
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#define S5P_SUBSAMPLING_MODE_422 (0x1 << 0)
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#define S5P_SUBSAMPLING_MODE_420 (0x2 << 0)
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#define S5P_SUBSAMPLING_MODE_GRAY (0x3 << 0)
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/* JPEG operation status register */
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#define S5P_JPGOPR 0x04
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/* Quantization tables*/
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#define S5P_JPG_QTBL 0x08
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#define S5P_QT_NUMt_SHIFT(t) (((t) - 1) << 1)
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#define S5P_QT_NUMt_MASK(t) (0x3 << S5P_QT_NUMt_SHIFT(t))
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/* Huffman tables */
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#define S5P_JPG_HTBL 0x0c
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#define S5P_HT_NUMt_AC_SHIFT(t) (((t) << 1) - 1)
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#define S5P_HT_NUMt_AC_MASK(t) (0x1 << S5P_HT_NUMt_AC_SHIFT(t))
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#define S5P_HT_NUMt_DC_SHIFT(t) (((t) - 1) << 1)
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#define S5P_HT_NUMt_DC_MASK(t) (0x1 << S5P_HT_NUMt_DC_SHIFT(t))
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/* JPEG restart interval register upper byte */
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#define S5P_JPGDRI_U 0x10
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/* JPEG restart interval register lower byte */
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#define S5P_JPGDRI_L 0x14
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/* JPEG vertical resolution register upper byte */
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#define S5P_JPGY_U 0x18
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/* JPEG vertical resolution register lower byte */
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#define S5P_JPGY_L 0x1c
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/* JPEG horizontal resolution register upper byte */
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#define S5P_JPGX_U 0x20
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/* JPEG horizontal resolution register lower byte */
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#define S5P_JPGX_L 0x24
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/* JPEG byte count register upper byte */
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#define S5P_JPGCNT_U 0x28
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/* JPEG byte count register middle byte */
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#define S5P_JPGCNT_M 0x2c
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/* JPEG byte count register lower byte */
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#define S5P_JPGCNT_L 0x30
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/* JPEG interrupt setting register */
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#define S5P_JPGINTSE 0x34
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#define S5P_RSTm_INT_EN_MASK (0x1 << 7)
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#define S5P_RSTm_INT_EN (0x1 << 7)
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#define S5P_DATA_NUM_INT_EN_MASK (0x1 << 6)
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#define S5P_DATA_NUM_INT_EN (0x1 << 6)
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#define S5P_FINAL_MCU_NUM_INT_EN_MASK (0x1 << 5)
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#define S5P_FINAL_MCU_NUM_INT_EN (0x1 << 5)
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/* JPEG interrupt status register */
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#define S5P_JPGINTST 0x38
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#define S5P_RESULT_STAT_SHIFT 6
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#define S5P_RESULT_STAT_MASK (0x1 << S5P_RESULT_STAT_SHIFT)
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#define S5P_STREAM_STAT_SHIFT 5
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#define S5P_STREAM_STAT_MASK (0x1 << S5P_STREAM_STAT_SHIFT)
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/* JPEG command register */
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#define S5P_JPGCOM 0x4c
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#define S5P_INT_RELEASE (0x1 << 2)
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/* Raw image data r/w address register */
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#define S5P_JPG_IMGADR 0x50
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/* JPEG file r/w address register */
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#define S5P_JPG_JPGADR 0x58
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/* Coefficient for RGB-to-YCbCr converter register */
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#define S5P_JPG_COEF(n) (0x5c + (((n) - 1) << 2))
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#define S5P_COEFn_SHIFT(j) ((3 - (j)) << 3)
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#define S5P_COEFn_MASK(j) (0xff << S5P_COEFn_SHIFT(j))
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/* JPEG color mode register */
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#define S5P_JPGCMOD 0x68
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#define S5P_MOD_SEL_MASK (0x7 << 5)
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#define S5P_MOD_SEL_422 (0x1 << 5)
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#define S5P_MOD_SEL_565 (0x2 << 5)
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#define S5P_MODE_Y16_MASK (0x1 << 1)
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#define S5P_MODE_Y16 (0x1 << 1)
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/* JPEG clock control register */
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#define S5P_JPGCLKCON 0x6c
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#define S5P_CLK_DOWN_READY (0x1 << 1)
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#define S5P_POWER_ON (0x1 << 0)
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/* JPEG start register */
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#define S5P_JSTART 0x70
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/* JPEG SW reset register */
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#define S5P_JPG_SW_RESET 0x78
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/* JPEG timer setting register */
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#define S5P_JPG_TIMER_SE 0x7c
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#define S5P_TIMER_INT_EN_MASK (0x1 << 31)
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#define S5P_TIMER_INT_EN (0x1 << 31)
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#define S5P_TIMER_INIT_MASK 0x7fffffff
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/* JPEG timer status register */
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#define S5P_JPG_TIMER_ST 0x80
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#define S5P_TIMER_INT_STAT_SHIFT 31
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#define S5P_TIMER_INT_STAT_MASK (0x1 << S5P_TIMER_INT_STAT_SHIFT)
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#define S5P_TIMER_CNT_SHIFT 0
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#define S5P_TIMER_CNT_MASK 0x7fffffff
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/* JPEG decompression output format register */
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#define S5P_JPG_OUTFORM 0x88
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#define S5P_DEC_OUT_FORMAT_MASK (0x1 << 0)
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#define S5P_DEC_OUT_FORMAT_422 (0x0 << 0)
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#define S5P_DEC_OUT_FORMAT_420 (0x1 << 0)
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/* JPEG version register */
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#define S5P_JPG_VERSION 0x8c
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/* JPEG compressed stream size interrupt setting register */
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#define S5P_JPG_ENC_STREAM_INTSE 0x98
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#define S5P_ENC_STREAM_INT_MASK (0x1 << 24)
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#define S5P_ENC_STREAM_INT_EN (0x1 << 24)
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#define S5P_ENC_STREAM_BOUND_MASK 0xffffff
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/* JPEG compressed stream size interrupt status register */
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#define S5P_JPG_ENC_STREAM_INTST 0x9c
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#define S5P_ENC_STREAM_INT_STAT_MASK 0x1
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/* JPEG quantizer table register */
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#define S5P_JPG_QTBL_CONTENT(n) (0x400 + (n) * 0x100)
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/* JPEG DC Huffman table register */
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#define S5P_JPG_HDCTBL(n) (0x800 + (n) * 0x400)
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/* JPEG DC Huffman table register */
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#define S5P_JPG_HDCTBLG(n) (0x840 + (n) * 0x400)
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/* JPEG AC Huffman table register */
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#define S5P_JPG_HACTBL(n) (0x880 + (n) * 0x400)
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/* JPEG AC Huffman table register */
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#define S5P_JPG_HACTBLG(n) (0x8c0 + (n) * 0x400)
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/* Register and bit definitions for Exynos 4x12 */
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/* JPEG Codec Control Registers */
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#define EXYNOS4_JPEG_CNTL_REG 0x00
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#define EXYNOS4_INT_EN_REG 0x04
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#define EXYNOS4_INT_TIMER_COUNT_REG 0x08
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#define EXYNOS4_INT_STATUS_REG 0x0c
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#define EXYNOS4_OUT_MEM_BASE_REG 0x10
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#define EXYNOS4_JPEG_IMG_SIZE_REG 0x14
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#define EXYNOS4_IMG_BA_PLANE_1_REG 0x18
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#define EXYNOS4_IMG_SO_PLANE_1_REG 0x1c
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#define EXYNOS4_IMG_PO_PLANE_1_REG 0x20
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#define EXYNOS4_IMG_BA_PLANE_2_REG 0x24
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#define EXYNOS4_IMG_SO_PLANE_2_REG 0x28
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#define EXYNOS4_IMG_PO_PLANE_2_REG 0x2c
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#define EXYNOS4_IMG_BA_PLANE_3_REG 0x30
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#define EXYNOS4_IMG_SO_PLANE_3_REG 0x34
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#define EXYNOS4_IMG_PO_PLANE_3_REG 0x38
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#define EXYNOS4_TBL_SEL_REG 0x3c
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#define EXYNOS4_IMG_FMT_REG 0x40
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#define EXYNOS4_BITSTREAM_SIZE_REG 0x44
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#define EXYNOS4_PADDING_REG 0x48
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#define EXYNOS4_HUFF_CNT_REG 0x4c
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#define EXYNOS4_FIFO_STATUS_REG 0x50
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#define EXYNOS4_DECODE_XY_SIZE_REG 0x54
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#define EXYNOS4_DECODE_IMG_FMT_REG 0x58
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#define EXYNOS4_QUAN_TBL_ENTRY_REG 0x100
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#define EXYNOS4_HUFF_TBL_ENTRY_REG 0x200
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/****************************************************************/
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/* Bit definition part */
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/****************************************************************/
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/* JPEG CNTL Register bit */
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#define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0)
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#define EXYNOS4_DEC_MODE (1 << 0)
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#define EXYNOS4_ENC_MODE (1 << 1)
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#define EXYNOS4_AUTO_RST_MARKER (1 << 2)
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#define EXYNOS4_RST_INTERVAL_SHIFT 3
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#define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \
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<< EXYNOS4_RST_INTERVAL_SHIFT)
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#define EXYNOS4_HUF_TBL_EN (1 << 19)
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#define EXYNOS4_HOR_SCALING_SHIFT 20
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#define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT)
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#define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \
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<< EXYNOS4_HOR_SCALING_SHIFT)
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#define EXYNOS4_VER_SCALING_SHIFT 22
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#define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT)
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#define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \
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<< EXYNOS4_VER_SCALING_SHIFT)
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#define EXYNOS4_PADDING (1 << 27)
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#define EXYNOS4_SYS_INT_EN (1 << 28)
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#define EXYNOS4_SOFT_RESET_HI (1 << 29)
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/* JPEG INT Register bit */
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#define EXYNOS4_INT_EN_MASK (0x1f << 0)
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#define EXYNOS4_PROT_ERR_INT_EN (1 << 0)
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#define EXYNOS4_IMG_COMPLETION_INT_EN (1 << 1)
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#define EXYNOS4_DEC_INVALID_FORMAT_EN (1 << 2)
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#define EXYNOS4_MULTI_SCAN_ERROR_EN (1 << 3)
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#define EXYNOS4_FRAME_ERR_EN (1 << 4)
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#define EXYNOS4_INT_EN_ALL (0x1f << 0)
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#define EXYNOS4_MOD_REG_PROC_ENC (0 << 3)
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#define EXYNOS4_MOD_REG_PROC_DEC (1 << 3)
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#define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0)
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#define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0)
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#define EXYNOS4_MOD_REG_SUBSAMPLE_420 (2 << 0)
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#define EXYNOS4_MOD_REG_SUBSAMPLE_GRAY (3 << 0)
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/* JPEG IMAGE SIZE Register bit */
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#define EXYNOS4_X_SIZE_SHIFT 0
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#define EXYNOS4_X_SIZE_MASK (0xffff << EXYNOS4_X_SIZE_SHIFT)
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#define EXYNOS4_X_SIZE(x) (((x) & 0xffff) << EXYNOS4_X_SIZE_SHIFT)
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#define EXYNOS4_Y_SIZE_SHIFT 16
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#define EXYNOS4_Y_SIZE_MASK (0xffff << EXYNOS4_Y_SIZE_SHIFT)
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#define EXYNOS4_Y_SIZE(x) (((x) & 0xffff) << EXYNOS4_Y_SIZE_SHIFT)
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/* JPEG IMAGE FORMAT Register bit */
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#define EXYNOS4_ENC_IN_FMT_MASK 0xffff0000
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#define EXYNOS4_ENC_GRAY_IMG (0 << 0)
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#define EXYNOS4_ENC_RGB_IMG (1 << 0)
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#define EXYNOS4_ENC_YUV_444_IMG (2 << 0)
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#define EXYNOS4_ENC_YUV_422_IMG (3 << 0)
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#define EXYNOS4_ENC_YUV_440_IMG (4 << 0)
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#define EXYNOS4_DEC_GRAY_IMG (0 << 0)
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#define EXYNOS4_DEC_RGB_IMG (1 << 0)
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#define EXYNOS4_DEC_YUV_444_IMG (2 << 0)
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#define EXYNOS4_DEC_YUV_422_IMG (3 << 0)
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#define EXYNOS4_DEC_YUV_420_IMG (4 << 0)
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#define EXYNOS4_GRAY_IMG_IP_SHIFT 3
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#define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT)
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#define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT)
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#define EXYNOS4_RGB_IP_SHIFT 6
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#define EXYNOS4_RGB_IP_MASK (7 << EXYNOS4_RGB_IP_SHIFT)
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#define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT)
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#define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT)
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#define EXYNOS4_YUV_444_IP_SHIFT 9
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#define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT)
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#define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT)
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#define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT)
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#define EXYNOS4_YUV_422_IP_SHIFT 12
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#define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT)
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#define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT)
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#define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT)
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#define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT)
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#define EXYNOS4_YUV_420_IP_SHIFT 15
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#define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT)
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#define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT)
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#define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT)
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#define EXYNOS4_ENC_FMT_SHIFT 24
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#define EXYNOS4_ENC_FMT_MASK (3 << EXYNOS4_ENC_FMT_SHIFT)
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#define EXYNOS4_ENC_FMT_GRAY (0 << EXYNOS4_ENC_FMT_SHIFT)
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#define EXYNOS4_ENC_FMT_YUV_444 (1 << EXYNOS4_ENC_FMT_SHIFT)
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#define EXYNOS4_ENC_FMT_YUV_422 (2 << EXYNOS4_ENC_FMT_SHIFT)
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#define EXYNOS4_ENC_FMT_YUV_420 (3 << EXYNOS4_ENC_FMT_SHIFT)
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#define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03
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#define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26)
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#define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26)
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/* JPEG HUFF count Register bit */
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#define EXYNOS4_HUFF_COUNT_MASK 0xffff
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/* JPEG Decoded_img_x_y_size Register bit */
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#define EXYNOS4_DECODED_SIZE_MASK 0x0000ffff
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/* JPEG Decoded image format Register bit */
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#define EXYNOS4_DECODED_IMG_FMT_MASK 0x3
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/* JPEG TBL SEL Register bit */
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#define EXYNOS4_Q_TBL_COMP1_0 (0 << 0)
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#define EXYNOS4_Q_TBL_COMP1_1 (1 << 0)
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#define EXYNOS4_Q_TBL_COMP1_2 (2 << 0)
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#define EXYNOS4_Q_TBL_COMP1_3 (3 << 0)
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#define EXYNOS4_Q_TBL_COMP2_0 (0 << 2)
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#define EXYNOS4_Q_TBL_COMP2_1 (1 << 2)
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#define EXYNOS4_Q_TBL_COMP2_2 (2 << 2)
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#define EXYNOS4_Q_TBL_COMP2_3 (3 << 2)
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#define EXYNOS4_Q_TBL_COMP3_0 (0 << 4)
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#define EXYNOS4_Q_TBL_COMP3_1 (1 << 4)
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#define EXYNOS4_Q_TBL_COMP3_2 (2 << 4)
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#define EXYNOS4_Q_TBL_COMP3_3 (3 << 4)
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#define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_0 (0 << 6)
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#define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 (1 << 6)
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#define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_0 (2 << 6)
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#define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_1 (3 << 6)
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#define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 (0 << 8)
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#define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_1 (1 << 8)
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#define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_0 (2 << 8)
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#define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_1 (3 << 8)
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#define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_0 (0 << 10)
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#define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_1 (1 << 10)
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#define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_0 (2 << 10)
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#define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1 (3 << 10)
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/* JPEG quantizer table register */
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#define EXYNOS4_QTBL_CONTENT(n) (0x100 + (n) * 0x40)
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/* JPEG DC luminance (code length) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HDCLL 0x200
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/* JPEG DC luminance (values) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HDCLV 0x210
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/* JPEG DC chrominance (code length) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HDCCL 0x220
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/* JPEG DC chrominance (values) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HDCCV 0x230
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/* JPEG AC luminance (code length) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HACLL 0x240
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/* JPEG AC luminance (values) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HACLV 0x250
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/* JPEG AC chrominance (code length) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HACCL 0x300
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/* JPEG AC chrominance (values) Huffman table register */
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#define EXYNOS4_HUFF_TBL_HACCV 0x310
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#endif /* JPEG_REGS_H_ */
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