mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 19:36:39 +07:00
8a25a2fd12
This moves the 'cpu sysdev_class' over to a regular 'cpu' subsystem and converts the devices to regular devices. The sysdev drivers are implemented as subsystem interfaces now. After all sysdev classes are ported to regular driver core entities, the sysdev implementation will be entirely removed from the kernel. Userspace relies on events and generic sysfs subsystem infrastructure from sysdev devices, which are made available with this conversion. Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Borislav Petkov <bp@amd64.org> Cc: Tigran Aivazian <tigran@aivazian.fsnet.co.uk> Cc: Len Brown <lenb@kernel.org> Cc: Zhang Rui <rui.zhang@intel.com> Cc: Dave Jones <davej@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: "Srivatsa S. Bhat" <srivatsa.bhat@linux.vnet.ibm.com> Signed-off-by: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
407 lines
10 KiB
C
407 lines
10 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/seq_file.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/param.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <asm/setup.h>
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#include <asm/sysreg.h>
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static DEFINE_PER_CPU(struct cpu, cpu_devices);
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#ifdef CONFIG_PERFORMANCE_COUNTERS
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/*
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* XXX: If/when a SMP-capable implementation of AVR32 will ever be
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* made, we must make sure that the code executes on the correct CPU.
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*/
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static ssize_t show_pc0event(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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unsigned long pccr;
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pccr = sysreg_read(PCCR);
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return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
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}
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static ssize_t store_pc0event(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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unsigned long val;
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char *endp;
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val = simple_strtoul(buf, &endp, 0);
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if (endp == buf || val > 0x3f)
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return -EINVAL;
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val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff);
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sysreg_write(PCCR, val);
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return count;
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}
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static ssize_t show_pc0count(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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unsigned long pcnt0;
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pcnt0 = sysreg_read(PCNT0);
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return sprintf(buf, "%lu\n", pcnt0);
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}
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static ssize_t store_pc0count(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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unsigned long val;
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char *endp;
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val = simple_strtoul(buf, &endp, 0);
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if (endp == buf)
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return -EINVAL;
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sysreg_write(PCNT0, val);
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return count;
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}
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static ssize_t show_pc1event(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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unsigned long pccr;
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pccr = sysreg_read(PCCR);
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return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
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}
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static ssize_t store_pc1event(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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unsigned long val;
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char *endp;
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val = simple_strtoul(buf, &endp, 0);
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if (endp == buf || val > 0x3f)
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return -EINVAL;
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val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff);
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sysreg_write(PCCR, val);
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return count;
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}
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static ssize_t show_pc1count(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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unsigned long pcnt1;
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pcnt1 = sysreg_read(PCNT1);
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return sprintf(buf, "%lu\n", pcnt1);
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}
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static ssize_t store_pc1count(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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unsigned long val;
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char *endp;
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val = simple_strtoul(buf, &endp, 0);
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if (endp == buf)
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return -EINVAL;
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sysreg_write(PCNT1, val);
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return count;
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}
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static ssize_t show_pccycles(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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unsigned long pccnt;
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pccnt = sysreg_read(PCCNT);
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return sprintf(buf, "%lu\n", pccnt);
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}
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static ssize_t store_pccycles(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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unsigned long val;
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char *endp;
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val = simple_strtoul(buf, &endp, 0);
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if (endp == buf)
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return -EINVAL;
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sysreg_write(PCCNT, val);
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return count;
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}
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static ssize_t show_pcenable(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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unsigned long pccr;
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pccr = sysreg_read(PCCR);
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return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
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}
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static ssize_t store_pcenable(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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unsigned long pccr, val;
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char *endp;
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val = simple_strtoul(buf, &endp, 0);
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if (endp == buf)
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return -EINVAL;
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if (val)
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val = 1;
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pccr = sysreg_read(PCCR);
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pccr = (pccr & ~1UL) | val;
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sysreg_write(PCCR, pccr);
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return count;
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}
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static DEVICE_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
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static DEVICE_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
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static DEVICE_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
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static DEVICE_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
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static DEVICE_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
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static DEVICE_ATTR(pcenable, 0600, show_pcenable, store_pcenable);
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#endif /* CONFIG_PERFORMANCE_COUNTERS */
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static int __init topology_init(void)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct cpu *c = &per_cpu(cpu_devices, cpu);
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register_cpu(c, cpu);
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#ifdef CONFIG_PERFORMANCE_COUNTERS
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device_create_file(&c->dev, &dev_attr_pc0event);
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device_create_file(&c->dev, &dev_attr_pc0count);
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device_create_file(&c->dev, &dev_attr_pc1event);
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device_create_file(&c->dev, &dev_attr_pc1count);
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device_create_file(&c->dev, &dev_attr_pccycles);
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device_create_file(&c->dev, &dev_attr_pcenable);
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#endif
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}
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return 0;
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}
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subsys_initcall(topology_init);
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struct chip_id_map {
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u16 mid;
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u16 pn;
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const char *name;
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};
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static const struct chip_id_map chip_names[] = {
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{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
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};
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#define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
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static const char *cpu_names[] = {
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"Morgan",
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"AP7",
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};
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#define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
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static const char *arch_names[] = {
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"AVR32A",
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"AVR32B",
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};
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#define NR_ARCH_NAMES ARRAY_SIZE(arch_names)
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static const char *mmu_types[] = {
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"No MMU",
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"ITLB and DTLB",
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"Shared TLB",
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"MPU"
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};
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static const char *cpu_feature_flags[] = {
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"rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
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};
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static const char *get_chip_name(struct avr32_cpuinfo *cpu)
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{
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unsigned int i;
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unsigned int mid = avr32_get_manufacturer_id(cpu);
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unsigned int pn = avr32_get_product_number(cpu);
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for (i = 0; i < NR_CHIP_NAMES; i++) {
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if (chip_names[i].mid == mid && chip_names[i].pn == pn)
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return chip_names[i].name;
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}
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return "(unknown)";
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}
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void __init setup_processor(void)
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{
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unsigned long config0, config1;
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unsigned long features;
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unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
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unsigned device_id;
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unsigned tmp;
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unsigned i;
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config0 = sysreg_read(CONFIG0);
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config1 = sysreg_read(CONFIG1);
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cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
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cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
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arch_id = SYSREG_BFEXT(AT, config0);
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arch_rev = SYSREG_BFEXT(AR, config0);
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mmu_type = SYSREG_BFEXT(MMUT, config0);
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device_id = ocd_read(DID);
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boot_cpu_data.arch_type = arch_id;
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boot_cpu_data.cpu_type = cpu_id;
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boot_cpu_data.arch_revision = arch_rev;
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boot_cpu_data.cpu_revision = cpu_rev;
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boot_cpu_data.tlb_config = mmu_type;
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boot_cpu_data.device_id = device_id;
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tmp = SYSREG_BFEXT(ILSZ, config1);
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if (tmp) {
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boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
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boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
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boot_cpu_data.icache.linesz = 1 << (tmp + 1);
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}
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tmp = SYSREG_BFEXT(DLSZ, config1);
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if (tmp) {
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boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
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boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
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boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
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}
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if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) {
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printk ("Unknown CPU configuration (ID %02x, arch %02x), "
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"continuing anyway...\n",
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cpu_id, arch_id);
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return;
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}
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printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
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avr32_get_chip_revision(&boot_cpu_data) + 'A');
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printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
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cpu_names[cpu_id], cpu_id, cpu_rev,
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arch_names[arch_id], arch_rev);
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printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
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printk ("CPU: features:");
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features = 0;
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if (config0 & SYSREG_BIT(CONFIG0_R))
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features |= AVR32_FEATURE_RMW;
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if (config0 & SYSREG_BIT(CONFIG0_D))
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features |= AVR32_FEATURE_DSP;
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if (config0 & SYSREG_BIT(CONFIG0_S))
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features |= AVR32_FEATURE_SIMD;
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if (config0 & SYSREG_BIT(CONFIG0_O))
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features |= AVR32_FEATURE_OCD;
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if (config0 & SYSREG_BIT(CONFIG0_P))
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features |= AVR32_FEATURE_PCTR;
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if (config0 & SYSREG_BIT(CONFIG0_J))
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features |= AVR32_FEATURE_JAVA;
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if (config0 & SYSREG_BIT(CONFIG0_F))
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features |= AVR32_FEATURE_FPU;
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for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
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if (features & (1 << i))
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printk(" %s", cpu_feature_flags[i]);
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printk("\n");
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boot_cpu_data.features = features;
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}
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#ifdef CONFIG_PROC_FS
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static int c_show(struct seq_file *m, void *v)
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{
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unsigned int icache_size, dcache_size;
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unsigned int cpu = smp_processor_id();
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unsigned int freq;
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unsigned int i;
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icache_size = boot_cpu_data.icache.ways *
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boot_cpu_data.icache.sets *
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boot_cpu_data.icache.linesz;
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dcache_size = boot_cpu_data.dcache.ways *
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boot_cpu_data.dcache.sets *
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boot_cpu_data.dcache.linesz;
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seq_printf(m, "processor\t: %d\n", cpu);
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seq_printf(m, "chip type\t: %s revision %c\n",
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get_chip_name(&boot_cpu_data),
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avr32_get_chip_revision(&boot_cpu_data) + 'A');
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if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
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seq_printf(m, "cpu arch\t: %s revision %d\n",
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arch_names[boot_cpu_data.arch_type],
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boot_cpu_data.arch_revision);
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if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
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seq_printf(m, "cpu core\t: %s revision %d\n",
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cpu_names[boot_cpu_data.cpu_type],
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boot_cpu_data.cpu_revision);
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freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
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seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
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seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
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icache_size >> 10,
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boot_cpu_data.icache.ways,
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boot_cpu_data.icache.sets,
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boot_cpu_data.icache.linesz);
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seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
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dcache_size >> 10,
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boot_cpu_data.dcache.ways,
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boot_cpu_data.dcache.sets,
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boot_cpu_data.dcache.linesz);
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seq_printf(m, "features\t:");
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for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
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if (boot_cpu_data.features & (1 << i))
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seq_printf(m, " %s", cpu_feature_flags[i]);
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seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
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boot_cpu_data.loops_per_jiffy / (500000/HZ),
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(boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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#endif /* CONFIG_PROC_FS */
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