mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 16:36:47 +07:00
482997699e
Add a generic /memory node in each Tegra DTSI (with empty reg property,
to be overidden by each DTS) and set proper unit address for /memory
nodes to fix the DTC warnings:
arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
/memory: node has a reg or ranges property, but no unit name
The DTB after the change is the same as before except adding
unit-address to /memory node.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
535 lines
12 KiB
Plaintext
535 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include "tegra20.dtsi"
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/ {
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model = "Avionic Design Tamonten SOM";
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compatible = "ad,tamonten", "nvidia,tegra20";
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aliases {
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rtc0 = "/i2c@7000d000/tps6586x@34";
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rtc1 = "/rtc@7000e000";
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serial0 = &uartd;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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reg = <0x00000000 0x20000000>;
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};
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host1x@50000000 {
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hdmi@54280000 {
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vdd-supply = <&hdmi_vdd_reg>;
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pll-supply = <&hdmi_pll_reg>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
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GPIO_ACTIVE_HIGH>;
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};
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};
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pinmux@70000014 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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ata {
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nvidia,pins = "ata";
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nvidia,function = "ide";
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};
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atb {
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nvidia,pins = "atb", "gma", "gme";
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nvidia,function = "sdio4";
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};
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atc {
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nvidia,pins = "atc";
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nvidia,function = "nand";
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};
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atd {
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nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
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"spia", "spib", "spic";
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nvidia,function = "gmi";
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};
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cdev1 {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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};
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cdev2 {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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};
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crtp {
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nvidia,pins = "crtp";
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nvidia,function = "crt";
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};
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csus {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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};
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dap1 {
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nvidia,pins = "dap1";
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nvidia,function = "dap1";
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};
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dap2 {
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nvidia,pins = "dap2";
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nvidia,function = "dap2";
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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};
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dap4 {
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nvidia,pins = "dap4";
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nvidia,function = "dap4";
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};
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dta {
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nvidia,pins = "dta", "dtd";
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nvidia,function = "sdio2";
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};
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dtb {
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nvidia,pins = "dtb", "dtc", "dte";
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nvidia,function = "rsvd1";
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};
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dtf {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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};
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gmc {
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nvidia,pins = "gmc";
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nvidia,function = "uartd";
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};
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gpu7 {
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nvidia,pins = "gpu7";
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nvidia,function = "rtck";
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};
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gpv {
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nvidia,pins = "gpv", "slxa", "slxk";
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nvidia,function = "pcie";
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};
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hdint {
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nvidia,pins = "hdint";
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nvidia,function = "hdmi";
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};
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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};
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irrx {
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nvidia,pins = "irrx", "irtx";
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nvidia,function = "uarta";
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};
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kbca {
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nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "kbc";
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};
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lcsn {
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nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
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"ld3", "ld4", "ld5", "ld6", "ld7",
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"ld8", "ld9", "ld10", "ld11", "ld12",
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"ld13", "ld14", "ld15", "ld16", "ld17",
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"ldc", "ldi", "lhp0", "lhp1", "lhp2",
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"lhs", "lm0", "lm1", "lpp", "lpw0",
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"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
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"lsda", "lsdi", "lspi", "lvp0", "lvp1",
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"lvs";
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nvidia,function = "displaya";
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};
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owc {
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nvidia,pins = "owc", "spdi", "spdo", "uac";
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nvidia,function = "rsvd2";
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};
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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};
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rm {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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};
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sdb {
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nvidia,pins = "sdb", "sdc", "sdd";
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nvidia,function = "pwm";
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};
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sdio1 {
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nvidia,pins = "sdio1";
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nvidia,function = "sdio1";
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};
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slxc {
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nvidia,pins = "slxc", "slxd";
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nvidia,function = "spdif";
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};
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spid {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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};
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spig {
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nvidia,pins = "spig", "spih";
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nvidia,function = "spi2_alt";
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};
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uaa {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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};
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uad {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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};
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uca {
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nvidia,pins = "uca", "ucb";
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nvidia,function = "uartc";
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};
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conf_ata {
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nvidia,pins = "ata", "atb", "atc", "atd", "ate",
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"cdev1", "cdev2", "dap1", "dtb", "gma",
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"gmb", "gmc", "gmd", "gme", "gpu7",
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"gpv", "i2cp", "pta", "rm", "slxa",
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"slxk", "spia", "spib", "uac";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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conf_ck32 {
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nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
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"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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conf_csus {
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nvidia,pins = "csus", "spid", "spif";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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conf_crtp {
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nvidia,pins = "crtp", "dap2", "dap3", "dap4",
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"dtc", "dte", "dtf", "gpu", "sdio1",
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"slxc", "slxd", "spdi", "spdo", "spig",
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"uda";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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conf_ddc {
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nvidia,pins = "ddc", "dta", "dtd", "kbca",
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"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
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"sdc";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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conf_hdint {
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nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
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"lpw1", "lsc1", "lsck", "lsda", "lsdi",
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"lvp0", "owc", "sdb";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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conf_irrx {
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nvidia,pins = "irrx", "irtx", "sdd", "spic",
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"spie", "spih", "uaa", "uab", "uad",
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"uca", "ucb";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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conf_lc {
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nvidia,pins = "lc", "ls";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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};
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conf_ld0 {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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"ld5", "ld6", "ld7", "ld8", "ld9",
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"ld10", "ld11", "ld12", "ld13", "ld14",
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"ld15", "ld16", "ld17", "ldi", "lhp0",
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"lhp1", "lhp2", "lhs", "lm0", "lpp",
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"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
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"lvs", "pmc";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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conf_ld17_0 {
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nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
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"ld23_22";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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};
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};
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state_i2cmux_ddc: pinmux_i2cmux_ddc {
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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};
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pta {
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nvidia,pins = "pta";
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nvidia,function = "rsvd4";
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};
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};
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state_i2cmux_pta: pinmux_i2cmux_pta {
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "rsvd4";
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};
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pta {
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nvidia,pins = "pta";
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nvidia,function = "i2c2";
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};
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};
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state_i2cmux_idle: pinmux_i2cmux_idle {
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "rsvd4";
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};
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pta {
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nvidia,pins = "pta";
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nvidia,function = "rsvd4";
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};
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};
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};
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i2s@70002800 {
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status = "okay";
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};
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serial@70006300 {
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status = "okay";
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};
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i2c@7000c000 {
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clock-frequency = <400000>;
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status = "okay";
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};
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i2c@7000c400 {
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clock-frequency = <100000>;
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status = "okay";
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};
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i2cmux {
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&{/i2c@7000c400}>;
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pinctrl-names = "ddc", "pta", "idle";
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pinctrl-0 = <&state_i2cmux_ddc>;
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pinctrl-1 = <&state_i2cmux_pta>;
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pinctrl-2 = <&state_i2cmux_idle>;
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hdmi_ddc: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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i2c@7000d000 {
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clock-frequency = <400000>;
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status = "okay";
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pmic: tps6586x@34 {
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compatible = "ti,tps6586x";
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reg = <0x34>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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ti,system-power-controller;
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#gpio-cells = <2>;
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gpio-controller;
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/* vdd_5v0_reg must be provided by the base board */
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sys-supply = <&vdd_5v0_reg>;
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vin-sm0-supply = <&sys_reg>;
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vin-sm1-supply = <&sys_reg>;
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vin-sm2-supply = <&sys_reg>;
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vinldo01-supply = <&sm2_reg>;
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vinldo23-supply = <&sm2_reg>;
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vinldo4-supply = <&sm2_reg>;
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vinldo678-supply = <&sm2_reg>;
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vinldo9-supply = <&sm2_reg>;
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regulators {
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sys_reg: sys {
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regulator-name = "vdd_sys";
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regulator-always-on;
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};
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sm0 {
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regulator-name = "vdd_sys_sm0,vdd_core";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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sm1 {
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regulator-name = "vdd_sys_sm1,vdd_cpu";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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sm2_reg: sm2 {
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regulator-name = "vdd_sys_sm2,vin_ldo*";
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regulator-min-microvolt = <3700000>;
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regulator-max-microvolt = <3700000>;
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regulator-always-on;
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};
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pci_clk_reg: ldo0 {
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regulator-name = "vdd_ldo0,vddio_pex_clk";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo1 {
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regulator-name = "vdd_ldo1,avdd_pll*";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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ldo2 {
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regulator-name = "vdd_ldo2,vdd_rtc";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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ldo3 {
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regulator-name = "vdd_ldo3,avdd_usb*";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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ldo4 {
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regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo5 {
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regulator-name = "vdd_ldo5,vcore_mmc";
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <2850000>;
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};
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ldo6 {
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regulator-name = "vdd_ldo6,avdd_vdac";
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/*
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* According to the Tegra 2 Automotive
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* DataSheet, a typical value for this
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* would be 2.8V, but the PMIC only
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* supports 2.85V.
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*/
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <2850000>;
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};
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hdmi_vdd_reg: ldo7 {
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regulator-name = "vdd_ldo7,avdd_hdmi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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hdmi_pll_reg: ldo8 {
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regulator-name = "vdd_ldo8,avdd_hdmi_pll";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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ldo9 {
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regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
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/*
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* According to the Tegra 2 Automotive
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* DataSheet, a typical value for this
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* would be 2.8V, but the PMIC only
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* supports 2.85V.
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*/
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <2850000>;
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regulator-always-on;
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};
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ldo_rtc {
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regulator-name = "vdd_rtc_out";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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temperature-sensor@4c {
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compatible = "onnn,nct1008";
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reg = <0x4c>;
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};
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};
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pmc@7000e400 {
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <5000>;
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nvidia,cpu-pwr-off-time = <5000>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <3875>;
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nvidia,sys-clock-req-active-high;
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};
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pcie@80003000 {
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avdd-pex-supply = <&pci_vdd_reg>;
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vdd-pex-supply = <&pci_vdd_reg>;
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avdd-pex-pll-supply = <&pci_vdd_reg>;
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avdd-plle-supply = <&pci_vdd_reg>;
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vddio-pex-clk-supply = <&pci_clk_reg>;
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};
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usb@c5008000 {
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status = "okay";
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};
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usb-phy@c5008000 {
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status = "okay";
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
|
|
bus-width = <4>;
|
|
status = "okay";
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk32k_in: clock@0 {
|
|
compatible = "fixed-clock";
|
|
reg = <0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pci_vdd_reg: regulator@1 {
|
|
compatible = "regulator-fixed";
|
|
reg = <1>;
|
|
regulator-name = "vdd_1v05";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
gpio = <&pmic 2 0>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
};
|