mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4fd5f8267d
Manual #include fixups for clashes - there may be some unnecessary
513 lines
13 KiB
C
513 lines
13 KiB
C
/*
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* arch/ppc/platforms/ev64360.c
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*
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* Board setup routines for the Marvell EV-64360-BP Evaluation Board.
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*
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* Author: Lee Nicks <allinux@gmail.com>
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*
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* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
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* Based on code done by - Mark A. Greer <mgreer@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/console.h>
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#include <linux/initrd.h>
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#include <linux/root_dev.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/bootmem.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx.h>
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#include <linux/platform_device.h>
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#ifdef CONFIG_BOOTIMG
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#include <linux/bootimg.h>
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#endif
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/smp.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/ppcboot.h>
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#include <asm/mv64x60.h>
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#include <asm/machdep.h>
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#include <platforms/ev64360.h>
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#define BOARD_VENDOR "Marvell"
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#define BOARD_MACHINE "EV-64360-BP"
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static struct mv64x60_handle bh;
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static void __iomem *sram_base;
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static u32 ev64360_flash_size_0;
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static u32 ev64360_flash_size_1;
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static u32 ev64360_bus_frequency;
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unsigned char __res[sizeof(bd_t)];
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static int __init
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ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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return 0;
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}
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static void __init
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ev64360_setup_bridge(void)
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{
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struct mv64x60_setup_info si;
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int i;
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memset(&si, 0, sizeof(si));
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si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
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#ifdef CONFIG_PCI
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si.pci_1.enable_bus = 1;
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si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
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si.pci_1.pci_io.pci_base_hi = 0;
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si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
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si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
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si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
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si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
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si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
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si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
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si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
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si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
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si.pci_1.pci_cmd_bits = 0;
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si.pci_1.latency_timer = 0x80;
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#else
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si.pci_0.enable_bus = 0;
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si.pci_1.enable_bus = 0;
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#endif
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for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
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#if defined(CONFIG_NOT_COHERENT_CACHE)
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si.cpu_prot_options[i] = 0;
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si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
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si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
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si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
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si.pci_1.acc_cntl_options[i] =
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MV64360_PCI_ACC_CNTL_SNOOP_NONE |
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MV64360_PCI_ACC_CNTL_SWAP_NONE |
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MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
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MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
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#else
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si.cpu_prot_options[i] = 0;
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si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
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si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
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si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
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si.pci_1.acc_cntl_options[i] =
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MV64360_PCI_ACC_CNTL_SNOOP_WB |
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MV64360_PCI_ACC_CNTL_SWAP_NONE |
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MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
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MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
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#endif
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}
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if (mv64x60_init(&bh, &si))
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printk(KERN_WARNING "Bridge initialization failed.\n");
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#ifdef CONFIG_PCI
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pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = ev64360_map_irq;
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ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
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mv64x60_set_bus(&bh, 1, 0);
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bh.hose_b->first_busno = 0;
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bh.hose_b->last_busno = 0xff;
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#endif
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}
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/* Bridge & platform setup routines */
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void __init
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ev64360_intr_setup(void)
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{
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/* MPP 8, 9, and 10 */
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mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
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/*
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* Define GPP 8,9,and 10 interrupt polarity as active low
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* input signal and level triggered
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*/
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mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
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mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
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/* Config GPP intr ctlr to respond to level trigger */
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mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
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/* Erranum FEr PCI-#8 */
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mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
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mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
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/*
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* Dismiss and then enable interrupt on GPP interrupt cause
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* for CPU #0
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*/
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mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
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mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
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/*
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* Dismiss and then enable interrupt on CPU #0 high cause reg
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* BIT25 summarizes GPP interrupts 8-15
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*/
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mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
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}
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void __init
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ev64360_setup_peripherals(void)
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{
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u32 base;
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/* Set up window for boot CS */
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
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EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
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/* We only use the 32-bit flash */
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mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
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&ev64360_flash_size_0);
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ev64360_flash_size_1 = 0;
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
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EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
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EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
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sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
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/* Set up Enet->SRAM window */
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mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
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EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
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bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
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/* Give enet r/w access to memory region */
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mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
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mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
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mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
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mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
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mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
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((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
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#if defined(CONFIG_NOT_COHERENT_CACHE)
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mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
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#else
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mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
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#endif
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/*
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* Setting the SRAM to 0. Note that this generates parity errors on
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* internal data path in SRAM since it's first time accessing it
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* while after reset it's not configured.
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*/
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memset(sram_base, 0, MV64360_SRAM_SIZE);
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/* set up PCI interrupt controller */
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ev64360_intr_setup();
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}
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static void __init
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ev64360_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("ev64360_setup_arch: enter", 0);
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set_tb(0, 0);
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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/*
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* Set up the L2CR register.
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*/
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_set_L2CR(L2CR_L2E | L2CR_L2PE);
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if (ppc_md.progress)
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ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
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ev64360_setup_bridge();
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ev64360_setup_peripherals();
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ev64360_bus_frequency = ev64360_bus_freq();
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printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
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"(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
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if (ppc_md.progress)
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ppc_md.progress("ev64360_setup_arch: exit", 0);
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}
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/* Platform device data fixup routines. */
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#if defined(CONFIG_SERIAL_MPSC)
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static void __init
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ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
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{
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struct mpsc_pdata *pdata;
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pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
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pdata->max_idle = 40;
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pdata->default_baud = EV64360_DEFAULT_BAUD;
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pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
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/*
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* TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
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* TCLK == SysCLK but on 64460, they are separate pins.
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* SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
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*/
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pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
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}
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#endif
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#if defined(CONFIG_MV643XX_ETH)
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static void __init
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ev64360_fixup_eth_pdata(struct platform_device *pdev)
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{
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struct mv643xx_eth_platform_data *eth_pd;
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static u16 phy_addr[] = {
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EV64360_ETH0_PHY_ADDR,
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EV64360_ETH1_PHY_ADDR,
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EV64360_ETH2_PHY_ADDR,
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};
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eth_pd = pdev->dev.platform_data;
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eth_pd->force_phy_addr = 1;
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eth_pd->phy_addr = phy_addr[pdev->id];
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eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
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eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
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}
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#endif
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static int __init
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ev64360_platform_notify(struct device *dev)
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{
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static struct {
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char *bus_id;
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void ((*rtn)(struct platform_device *pdev));
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} dev_map[] = {
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#if defined(CONFIG_SERIAL_MPSC)
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{ MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
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{ MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
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#endif
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#if defined(CONFIG_MV643XX_ETH)
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{ MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
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{ MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
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{ MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
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#endif
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};
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struct platform_device *pdev;
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int i;
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if (dev && dev->bus_id)
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for (i=0; i<ARRAY_SIZE(dev_map); i++)
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if (!strncmp(dev->bus_id, dev_map[i].bus_id,
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BUS_ID_SIZE)) {
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pdev = container_of(dev,
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struct platform_device, dev);
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dev_map[i].rtn(pdev);
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}
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return 0;
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}
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#ifdef CONFIG_MTD_PHYSMAP
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#ifndef MB
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#define MB (1 << 20)
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#endif
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/*
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* MTD Layout.
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*
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* FLASH Amount: 0xff000000 - 0xffffffff
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* ------------- -----------------------
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* Reserved: 0xff000000 - 0xff03ffff
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* JFFS2 file system: 0xff040000 - 0xffefffff
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* U-boot: 0xfff00000 - 0xffffffff
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*/
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static int __init
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ev64360_setup_mtd(void)
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{
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u32 size;
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int ptbl_entries;
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static struct mtd_partition *ptbl;
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size = ev64360_flash_size_0 + ev64360_flash_size_1;
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if (!size)
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return -ENOMEM;
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ptbl_entries = 3;
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if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
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GFP_KERNEL)) == NULL) {
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printk(KERN_WARNING "Can't alloc MTD partition table\n");
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return -ENOMEM;
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}
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memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
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ptbl[0].name = "reserved";
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ptbl[0].offset = 0;
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ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
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ptbl[1].name = "jffs2";
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ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
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ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
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ptbl[2].name = "U-BOOT";
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ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
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ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
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physmap_map.size = size;
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physmap_set_partitions(ptbl, ptbl_entries);
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return 0;
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}
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arch_initcall(ev64360_setup_mtd);
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#endif
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static void
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ev64360_restart(char *cmd)
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{
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ulong i = 0xffffffff;
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volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
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/* issue hard reset */
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rtc_base[0xf] = 0x80;
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rtc_base[0xc] = 0x00;
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rtc_base[0xd] = 0x01;
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rtc_base[0xf] = 0x83;
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while (i-- > 0) ;
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panic("restart failed\n");
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}
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static void
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ev64360_halt(void)
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{
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while (1) ;
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/* NOTREACHED */
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}
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static void
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ev64360_power_off(void)
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{
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ev64360_halt();
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/* NOTREACHED */
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}
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static int
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ev64360_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
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seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
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seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
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return 0;
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}
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static void __init
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ev64360_calibrate_decr(void)
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{
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u32 freq;
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freq = ev64360_bus_frequency / 4;
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printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
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(long)freq / 1000000, (long)freq % 1000000);
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tb_ticks_per_jiffy = freq / HZ;
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tb_to_us = mulhwu_scale_factor(freq, 1000000);
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}
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unsigned long __init
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ev64360_find_end_of_memory(void)
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{
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return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
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MV64x60_TYPE_MV64360);
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}
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static inline void
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ev64360_set_bat(void)
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{
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mb();
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mtspr(SPRN_DBAT2U, 0xf0001ffe);
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mtspr(SPRN_DBAT2L, 0xf000002a);
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mb();
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
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static void __init
|
|
ev64360_map_io(void)
|
|
{
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|
io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
|
|
CONFIG_MV64X60_NEW_BASE, \
|
|
0x00020000, _PAGE_IO);
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|
}
|
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#endif
|
|
|
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void __init
|
|
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7)
|
|
{
|
|
parse_bootinfo(find_bootinfo());
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|
|
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/* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
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|
* are non-zero, then we should use the board info from the bd_t
|
|
* structure and the cmdline pointed to by r6 instead of the
|
|
* information from birecs, if any. Otherwise, use the information
|
|
* from birecs as discovered by the preceeding call to
|
|
* parse_bootinfo(). This rule should work with both PPCBoot, which
|
|
* uses a bd_t board info structure, and the kernel boot wrapper,
|
|
* which uses birecs.
|
|
*/
|
|
if (r3 && r6) {
|
|
/* copy board info structure */
|
|
memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
|
|
/* copy command line */
|
|
*(char *)(r7+KERNELBASE) = 0;
|
|
strcpy(cmd_line, (char *)(r6+KERNELBASE));
|
|
}
|
|
#ifdef CONFIG_ISA
|
|
isa_mem_base = 0;
|
|
#endif
|
|
|
|
ppc_md.setup_arch = ev64360_setup_arch;
|
|
ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
|
|
ppc_md.init_IRQ = mv64360_init_irq;
|
|
ppc_md.get_irq = mv64360_get_irq;
|
|
ppc_md.restart = ev64360_restart;
|
|
ppc_md.power_off = ev64360_power_off;
|
|
ppc_md.halt = ev64360_halt;
|
|
ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
|
|
ppc_md.calibrate_decr = ev64360_calibrate_decr;
|
|
|
|
#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
|
|
ppc_md.setup_io_mappings = ev64360_map_io;
|
|
ppc_md.progress = mv64x60_mpsc_progress;
|
|
mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
|
|
#endif
|
|
|
|
#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
|
|
platform_notify = ev64360_platform_notify;
|
|
#endif
|
|
|
|
ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
|
|
}
|