Florian Fainelli a5b143ec51 MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435 ... 7435 has 4 7038 L1 base register address for each of its Core + TP (for a total of 4 threads of execution), add the two missing cells for Core 1. We are providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they are, and we can later decide to remap these in software to provide proper interrupt affinity/parenting. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12378/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2016-05-09 12:00:01 +02:00
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compressed	MIPS: zboot: Remove copied source files on clean	2016-04-03 10:37:21 +02:00
dts	MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435	2016-05-09 12:00:01 +02:00
.gitignore	MIPS: Add support for building device-tree binaries	2014-09-22 13:35:49 +02:00
ecoff.h	MIPS: remove duplicate define	2013-11-06 15:51:19 +01:00
elf2ecoff.c	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	2015-02-21 19:41:38 -08:00
Makefile	MIPS: boot: Provide more uImage options	2015-02-20 14:17:43 +01:00