mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 00:17:40 +07:00
1d3fac0c2a
The hw doesn't really appear to be designed to be used the way we have to use it due to DRI2's design. This leads us to having to keep the flipped fb support active at all times. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
793 lines
21 KiB
C
793 lines
21 KiB
C
/*
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* Copyright (C) 2008 Maarten Maathuis.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm_mode.h"
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#include "drm_crtc_helper.h"
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#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
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#include "nouveau_reg.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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#include "nouveau_encoder.h"
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#include "nouveau_crtc.h"
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#include "nouveau_fb.h"
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#include "nouveau_connector.h"
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#include "nv50_display.h"
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static void
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nv50_crtc_lut_load(struct drm_crtc *crtc)
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{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
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int i;
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NV_DEBUG_KMS(crtc->dev, "\n");
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for (i = 0; i < 256; i++) {
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writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
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writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
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writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
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}
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if (nv_crtc->lut.depth == 30) {
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writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
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writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
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writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
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}
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}
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int
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nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
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{
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struct drm_device *dev = nv_crtc->base.dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *evo = nv50_display(dev)->master;
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int index = nv_crtc->index, ret;
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NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
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NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
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if (blanked) {
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nv_crtc->cursor.hide(nv_crtc, false);
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ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
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if (ret) {
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NV_ERROR(dev, "no space while blanking crtc\n");
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return ret;
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}
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
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OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
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OUT_RING(evo, 0);
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if (dev_priv->chipset != 0x50) {
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BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
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OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
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}
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
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OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
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} else {
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if (nv_crtc->cursor.visible)
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nv_crtc->cursor.show(nv_crtc, false);
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else
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nv_crtc->cursor.hide(nv_crtc, false);
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ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
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if (ret) {
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NV_ERROR(dev, "no space while unblanking crtc\n");
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return ret;
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}
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
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OUT_RING(evo, nv_crtc->lut.depth == 8 ?
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NV50_EVO_CRTC_CLUT_MODE_OFF :
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NV50_EVO_CRTC_CLUT_MODE_ON);
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OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.start << PAGE_SHIFT) >> 8);
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if (dev_priv->chipset != 0x50) {
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BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
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OUT_RING(evo, NvEvoVRAM);
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}
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
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OUT_RING(evo, nv_crtc->fb.offset >> 8);
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OUT_RING(evo, 0);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
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if (dev_priv->chipset != 0x50)
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if (nv_crtc->fb.tile_flags == 0x7a00 ||
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nv_crtc->fb.tile_flags == 0xfe00)
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OUT_RING(evo, NvEvoFB32);
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else
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if (nv_crtc->fb.tile_flags == 0x7000)
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OUT_RING(evo, NvEvoFB16);
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else
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OUT_RING(evo, NvEvoVRAM_LP);
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else
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OUT_RING(evo, NvEvoVRAM_LP);
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}
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nv_crtc->fb.blanked = blanked;
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return 0;
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}
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static int
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nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
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{
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struct drm_device *dev = nv_crtc->base.dev;
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struct nouveau_channel *evo = nv50_display(dev)->master;
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int ret;
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NV_DEBUG_KMS(dev, "\n");
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ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
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if (ret) {
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NV_ERROR(dev, "no space while setting dither\n");
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return ret;
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}
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
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if (on)
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OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
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else
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OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
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if (update) {
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BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
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OUT_RING(evo, 0);
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FIRE_RING(evo);
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}
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return 0;
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}
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struct nouveau_connector *
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nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
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{
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struct drm_device *dev = nv_crtc->base.dev;
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struct drm_connector *connector;
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struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
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/* The safest approach is to find an encoder with the right crtc, that
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* is also linked to a connector. */
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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if (connector->encoder)
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if (connector->encoder->crtc == crtc)
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return nouveau_connector(connector);
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}
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return NULL;
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}
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static int
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nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
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{
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struct nouveau_connector *nv_connector =
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nouveau_crtc_connector_get(nv_crtc);
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struct drm_device *dev = nv_crtc->base.dev;
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struct nouveau_channel *evo = nv50_display(dev)->master;
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struct drm_display_mode *native_mode = NULL;
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struct drm_display_mode *mode = &nv_crtc->base.mode;
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uint32_t outX, outY, horiz, vert;
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int ret;
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NV_DEBUG_KMS(dev, "\n");
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switch (scaling_mode) {
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case DRM_MODE_SCALE_NONE:
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break;
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default:
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if (!nv_connector || !nv_connector->native_mode) {
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NV_ERROR(dev, "No native mode, forcing panel scaling\n");
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scaling_mode = DRM_MODE_SCALE_NONE;
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} else {
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native_mode = nv_connector->native_mode;
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}
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break;
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}
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switch (scaling_mode) {
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case DRM_MODE_SCALE_ASPECT:
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horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
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vert = (native_mode->vdisplay << 19) / mode->vdisplay;
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if (vert > horiz) {
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outX = (mode->hdisplay * horiz) >> 19;
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outY = (mode->vdisplay * horiz) >> 19;
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} else {
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outX = (mode->hdisplay * vert) >> 19;
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outY = (mode->vdisplay * vert) >> 19;
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}
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break;
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case DRM_MODE_SCALE_FULLSCREEN:
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outX = native_mode->hdisplay;
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outY = native_mode->vdisplay;
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break;
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case DRM_MODE_SCALE_CENTER:
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case DRM_MODE_SCALE_NONE:
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default:
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outX = mode->hdisplay;
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outY = mode->vdisplay;
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break;
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}
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ret = RING_SPACE(evo, update ? 7 : 5);
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if (ret)
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return ret;
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/* Got a better name for SCALER_ACTIVE? */
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/* One day i've got to really figure out why this is needed. */
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
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if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
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(mode->flags & DRM_MODE_FLAG_INTERLACE) ||
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mode->hdisplay != outX || mode->vdisplay != outY) {
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OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
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} else {
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OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
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}
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
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OUT_RING(evo, outY << 16 | outX);
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OUT_RING(evo, outY << 16 | outX);
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if (update) {
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BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
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OUT_RING(evo, 0);
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FIRE_RING(evo);
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}
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return 0;
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}
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int
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nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct pll_lims pll;
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uint32_t reg1, reg2;
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int ret, N1, M1, N2, M2, P;
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ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll);
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if (ret)
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return ret;
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if (pll.vco2.maxfreq) {
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ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
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if (ret <= 0)
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return 0;
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NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
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pclk, ret, N1, M1, N2, M2, P);
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reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
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reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00;
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nv_wr32(dev, pll.reg + 0, 0x10000611);
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nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
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nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
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} else
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if (dev_priv->chipset < NV_C0) {
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ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
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if (ret <= 0)
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return 0;
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NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
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pclk, ret, N1, N2, M1, P);
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reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
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nv_wr32(dev, pll.reg + 0, 0x50000610);
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nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
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nv_wr32(dev, pll.reg + 8, N2);
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} else {
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ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
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if (ret <= 0)
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return 0;
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NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
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pclk, ret, N1, N2, M1, P);
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nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100);
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nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1);
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nv_wr32(dev, pll.reg + 0x10, N2 << 16);
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}
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return 0;
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}
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static void
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nv50_crtc_destroy(struct drm_crtc *crtc)
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{
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struct drm_device *dev;
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struct nouveau_crtc *nv_crtc;
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if (!crtc)
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return;
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dev = crtc->dev;
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nv_crtc = nouveau_crtc(crtc);
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NV_DEBUG_KMS(dev, "\n");
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drm_crtc_cleanup(&nv_crtc->base);
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nv50_cursor_fini(nv_crtc);
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nouveau_bo_unmap(nv_crtc->lut.nvbo);
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nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
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nouveau_bo_unmap(nv_crtc->cursor.nvbo);
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nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
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kfree(nv_crtc->mode);
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kfree(nv_crtc);
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}
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int
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nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
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uint32_t buffer_handle, uint32_t width, uint32_t height)
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{
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struct drm_device *dev = crtc->dev;
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nouveau_bo *cursor = NULL;
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struct drm_gem_object *gem;
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int ret = 0, i;
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if (width != 64 || height != 64)
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return -EINVAL;
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if (!buffer_handle) {
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nv_crtc->cursor.hide(nv_crtc, true);
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return 0;
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}
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gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
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if (!gem)
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return -ENOENT;
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cursor = nouveau_gem_object(gem);
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ret = nouveau_bo_map(cursor);
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if (ret)
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goto out;
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/* The simple will do for now. */
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for (i = 0; i < 64 * 64; i++)
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nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
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nouveau_bo_unmap(cursor);
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nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT);
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nv_crtc->cursor.show(nv_crtc, true);
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out:
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drm_gem_object_unreference_unlocked(gem);
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return ret;
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}
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int
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nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
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{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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nv_crtc->cursor.set_pos(nv_crtc, x, y);
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return 0;
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}
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static void
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nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
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uint32_t start, uint32_t size)
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{
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int end = (start + size > 256) ? 256 : start + size, i;
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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for (i = start; i < end; i++) {
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nv_crtc->lut.r[i] = r[i];
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nv_crtc->lut.g[i] = g[i];
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nv_crtc->lut.b[i] = b[i];
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}
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/* We need to know the depth before we upload, but it's possible to
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* get called before a framebuffer is bound. If this is the case,
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* mark the lut values as dirty by setting depth==0, and it'll be
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* uploaded on the first mode_set_base()
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*/
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if (!nv_crtc->base.fb) {
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nv_crtc->lut.depth = 0;
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return;
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}
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nv50_crtc_lut_load(crtc);
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}
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static void
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nv50_crtc_save(struct drm_crtc *crtc)
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{
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NV_ERROR(crtc->dev, "!!\n");
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}
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static void
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nv50_crtc_restore(struct drm_crtc *crtc)
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{
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NV_ERROR(crtc->dev, "!!\n");
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}
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static const struct drm_crtc_funcs nv50_crtc_funcs = {
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.save = nv50_crtc_save,
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.restore = nv50_crtc_restore,
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.cursor_set = nv50_crtc_cursor_set,
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.cursor_move = nv50_crtc_cursor_move,
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.gamma_set = nv50_crtc_gamma_set,
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.set_config = drm_crtc_helper_set_config,
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.page_flip = nouveau_crtc_page_flip,
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.destroy = nv50_crtc_destroy,
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};
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static void
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nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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}
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static int
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nv50_crtc_wait_complete(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
|
|
struct nv50_display *disp = nv50_display(dev);
|
|
struct nouveau_channel *evo = disp->master;
|
|
u64 start;
|
|
int ret;
|
|
|
|
ret = RING_SPACE(evo, 6);
|
|
if (ret)
|
|
return ret;
|
|
BEGIN_RING(evo, 0, 0x0084, 1);
|
|
OUT_RING (evo, 0x80000000);
|
|
BEGIN_RING(evo, 0, 0x0080, 1);
|
|
OUT_RING (evo, 0);
|
|
BEGIN_RING(evo, 0, 0x0084, 1);
|
|
OUT_RING (evo, 0x00000000);
|
|
|
|
nv_wo32(disp->ntfy, 0x000, 0x00000000);
|
|
FIRE_RING (evo);
|
|
|
|
start = ptimer->read(dev);
|
|
do {
|
|
nv_wr32(dev, 0x61002c, 0x370);
|
|
nv_wr32(dev, 0x000140, 1);
|
|
|
|
if (nv_ro32(disp->ntfy, 0x000))
|
|
return 0;
|
|
} while (ptimer->read(dev) - start < 2000000000ULL);
|
|
|
|
return -EBUSY;
|
|
}
|
|
|
|
static void
|
|
nv50_crtc_prepare(struct drm_crtc *crtc)
|
|
{
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
|
|
|
|
nv50_display_flip_stop(crtc);
|
|
drm_vblank_pre_modeset(dev, nv_crtc->index);
|
|
nv50_crtc_blank(nv_crtc, true);
|
|
}
|
|
|
|
static void
|
|
nv50_crtc_commit(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
|
|
|
|
nv50_crtc_blank(nv_crtc, false);
|
|
drm_vblank_post_modeset(dev, nv_crtc->index);
|
|
nv50_crtc_wait_complete(crtc);
|
|
nv50_display_flip_next(crtc, crtc->fb, NULL);
|
|
}
|
|
|
|
static bool
|
|
nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static int
|
|
nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *passed_fb,
|
|
int x, int y, bool atomic)
|
|
{
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
struct drm_device *dev = nv_crtc->base.dev;
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nouveau_channel *evo = nv50_display(dev)->master;
|
|
struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
|
|
struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
|
|
int ret;
|
|
|
|
NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
|
|
|
|
/* If atomic, we want to switch to the fb we were passed, so
|
|
* now we update pointers to do that. (We don't pin; just
|
|
* assume we're already pinned and update the base address.)
|
|
*/
|
|
if (atomic) {
|
|
drm_fb = passed_fb;
|
|
fb = nouveau_framebuffer(passed_fb);
|
|
}
|
|
else {
|
|
/* If not atomic, we can go ahead and pin, and unpin the
|
|
* old fb we were passed.
|
|
*/
|
|
ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (passed_fb) {
|
|
struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
|
|
nouveau_bo_unpin(ofb->nvbo);
|
|
}
|
|
}
|
|
|
|
nv_crtc->fb.offset = fb->nvbo->bo.mem.start << PAGE_SHIFT;
|
|
nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo);
|
|
nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
|
|
if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
|
|
ret = RING_SPACE(evo, 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
|
|
OUT_RING (evo, fb->r_dma);
|
|
}
|
|
|
|
ret = RING_SPACE(evo, 12);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
|
|
OUT_RING (evo, nv_crtc->fb.offset >> 8);
|
|
OUT_RING (evo, 0);
|
|
OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width);
|
|
OUT_RING (evo, fb->r_pitch);
|
|
OUT_RING (evo, fb->r_format);
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
|
|
OUT_RING (evo, fb->base.depth == 8 ?
|
|
NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
|
|
OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
|
|
OUT_RING (evo, (y << 16) | x);
|
|
|
|
if (nv_crtc->lut.depth != fb->base.depth) {
|
|
nv_crtc->lut.depth = fb->base.depth;
|
|
nv50_crtc_lut_load(crtc);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode, int x, int y,
|
|
struct drm_framebuffer *old_fb)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct nouveau_channel *evo = nv50_display(dev)->master;
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
struct nouveau_connector *nv_connector = NULL;
|
|
uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
|
|
uint32_t hunk1, vunk1, vunk2a, vunk2b;
|
|
int ret;
|
|
|
|
/* Find the connector attached to this CRTC */
|
|
nv_connector = nouveau_crtc_connector_get(nv_crtc);
|
|
|
|
*nv_crtc->mode = *adjusted_mode;
|
|
|
|
NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
|
|
|
|
hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
|
|
vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
|
|
hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
|
|
vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
|
|
/* I can't give this a proper name, anyone else can? */
|
|
hunk1 = adjusted_mode->htotal -
|
|
adjusted_mode->hsync_start + adjusted_mode->hdisplay;
|
|
vunk1 = adjusted_mode->vtotal -
|
|
adjusted_mode->vsync_start + adjusted_mode->vdisplay;
|
|
/* Another strange value, this time only for interlaced adjusted_modes. */
|
|
vunk2a = 2 * adjusted_mode->vtotal -
|
|
adjusted_mode->vsync_start + adjusted_mode->vdisplay;
|
|
vunk2b = adjusted_mode->vtotal -
|
|
adjusted_mode->vsync_start + adjusted_mode->vtotal;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
vsync_dur /= 2;
|
|
vsync_start_to_end /= 2;
|
|
vunk1 /= 2;
|
|
vunk2a /= 2;
|
|
vunk2b /= 2;
|
|
/* magic */
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
|
|
vsync_start_to_end -= 1;
|
|
vunk1 -= 1;
|
|
vunk2a -= 1;
|
|
vunk2b -= 1;
|
|
}
|
|
}
|
|
|
|
ret = RING_SPACE(evo, 17);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
|
|
OUT_RING(evo, adjusted_mode->clock | 0x800000);
|
|
OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
|
|
OUT_RING(evo, 0);
|
|
OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
|
|
OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
|
|
OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
|
|
(hsync_start_to_end - 1));
|
|
OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
|
|
OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
|
|
} else {
|
|
OUT_RING(evo, 0);
|
|
OUT_RING(evo, 0);
|
|
}
|
|
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
|
|
OUT_RING(evo, 0);
|
|
|
|
/* This is the actual resolution of the mode. */
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
|
|
OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
|
|
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
|
|
OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
|
|
|
|
nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
|
|
nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
|
|
|
|
return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
|
|
}
|
|
|
|
static int
|
|
nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
|
struct drm_framebuffer *old_fb)
|
|
{
|
|
int ret;
|
|
|
|
nv50_display_flip_stop(crtc);
|
|
ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nv50_crtc_wait_complete(crtc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return nv50_display_flip_next(crtc, crtc->fb, NULL);
|
|
}
|
|
|
|
static int
|
|
nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
int x, int y, enum mode_set_atomic state)
|
|
{
|
|
int ret;
|
|
|
|
nv50_display_flip_stop(crtc);
|
|
ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return nv50_crtc_wait_complete(crtc);
|
|
}
|
|
|
|
static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
|
|
.dpms = nv50_crtc_dpms,
|
|
.prepare = nv50_crtc_prepare,
|
|
.commit = nv50_crtc_commit,
|
|
.mode_fixup = nv50_crtc_mode_fixup,
|
|
.mode_set = nv50_crtc_mode_set,
|
|
.mode_set_base = nv50_crtc_mode_set_base,
|
|
.mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
|
|
.load_lut = nv50_crtc_lut_load,
|
|
};
|
|
|
|
int
|
|
nv50_crtc_create(struct drm_device *dev, int index)
|
|
{
|
|
struct nouveau_crtc *nv_crtc = NULL;
|
|
int ret, i;
|
|
|
|
NV_DEBUG_KMS(dev, "\n");
|
|
|
|
nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
|
|
if (!nv_crtc)
|
|
return -ENOMEM;
|
|
|
|
nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
|
|
if (!nv_crtc->mode) {
|
|
kfree(nv_crtc);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Default CLUT parameters, will be activated on the hw upon
|
|
* first mode set.
|
|
*/
|
|
for (i = 0; i < 256; i++) {
|
|
nv_crtc->lut.r[i] = i << 8;
|
|
nv_crtc->lut.g[i] = i << 8;
|
|
nv_crtc->lut.b[i] = i << 8;
|
|
}
|
|
nv_crtc->lut.depth = 0;
|
|
|
|
ret = nouveau_bo_new(dev, NULL, 4096, 0x100, TTM_PL_FLAG_VRAM,
|
|
0, 0x0000, false, true, &nv_crtc->lut.nvbo);
|
|
if (!ret) {
|
|
ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
|
|
if (!ret)
|
|
ret = nouveau_bo_map(nv_crtc->lut.nvbo);
|
|
if (ret)
|
|
nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
|
|
}
|
|
|
|
if (ret) {
|
|
kfree(nv_crtc->mode);
|
|
kfree(nv_crtc);
|
|
return ret;
|
|
}
|
|
|
|
nv_crtc->index = index;
|
|
|
|
/* set function pointers */
|
|
nv_crtc->set_dither = nv50_crtc_set_dither;
|
|
nv_crtc->set_scale = nv50_crtc_set_scale;
|
|
|
|
drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
|
|
drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
|
|
drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
|
|
|
|
ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
|
|
0, 0x0000, false, true, &nv_crtc->cursor.nvbo);
|
|
if (!ret) {
|
|
ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
|
|
if (!ret)
|
|
ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
|
|
if (ret)
|
|
nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
|
|
}
|
|
|
|
nv50_cursor_init(nv_crtc);
|
|
return 0;
|
|
}
|