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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 13:14:36 +07:00
863204cfda
In configurations without CONFIG_OMAP3 but with secure RAM support,
we now run into a link failure:
arch/arm/mach-omap2/omap-secure.o: In function `omap3_save_secure_ram':
omap-secure.c:(.text+0x130): undefined reference to `save_secure_ram_context'
The omap3_save_secure_ram() function is only called from the OMAP34xx
power management code, so we can simply hide that function in the
appropriate #ifdef.
Fixes: d09220a887 ("ARM: OMAP2+: Fix SRAM virt to phys translation for save_secure_ram_context")
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
170 lines
4.0 KiB
C
170 lines
4.0 KiB
C
/*
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* OMAP Secure API infrastructure.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
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* Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/memblock.h>
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#include <asm/cacheflush.h>
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#include <asm/memblock.h>
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#include "omap-secure.h"
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static phys_addr_t omap_secure_memblock_base;
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/**
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* omap_sec_dispatcher: Routine to dispatch low power secure
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* service routines
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* @idx: The HAL API index
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* @flag: The flag indicating criticality of operation
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* @nargs: Number of valid arguments out of four.
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* @arg1, arg2, arg3 args4: Parameters passed to secure API
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*
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* Return the non-zero error value on failure.
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*/
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u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
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u32 arg3, u32 arg4)
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{
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u32 ret;
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u32 param[5];
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param[0] = nargs;
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param[1] = arg1;
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param[2] = arg2;
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param[3] = arg3;
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param[4] = arg4;
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/*
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* Secure API needs physical address
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* pointer for the parameters
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*/
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flush_cache_all();
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outer_clean_range(__pa(param), __pa(param + 5));
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ret = omap_smc2(idx, flag, __pa(param));
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return ret;
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}
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/* Allocate the memory to save secure ram */
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int __init omap_secure_ram_reserve_memblock(void)
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{
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u32 size = OMAP_SECURE_RAM_STORAGE;
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size = ALIGN(size, SECTION_SIZE);
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omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
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return 0;
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}
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phys_addr_t omap_secure_ram_mempool_base(void)
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{
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return omap_secure_memblock_base;
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}
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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u32 omap3_save_secure_ram(void __iomem *addr, int size)
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{
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u32 ret;
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u32 param[5];
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if (size != OMAP3_SAVE_SECURE_RAM_SZ)
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return OMAP3_SAVE_SECURE_RAM_SZ;
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param[0] = 4; /* Number of arguments */
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param[1] = __pa(addr); /* Physical address for saving */
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param[2] = 0;
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param[3] = 1;
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param[4] = 1;
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ret = save_secure_ram_context(__pa(param));
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return ret;
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}
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#endif
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/**
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* rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
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* @idx: The PPA API index
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* @process: Process ID
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* @flag: The flag indicating criticality of operation
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* @nargs: Number of valid arguments out of four.
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* @arg1, arg2, arg3 args4: Parameters passed to secure API
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*
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* Return the non-zero error value on failure.
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*
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* NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
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* it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
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*/
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u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4)
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{
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u32 ret;
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u32 param[5];
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param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
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param[1] = arg1;
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param[2] = arg2;
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param[3] = arg3;
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param[4] = arg4;
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/*
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* Secure API needs physical address
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* pointer for the parameters
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*/
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local_irq_disable();
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local_fiq_disable();
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flush_cache_all();
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outer_clean_range(__pa(param), __pa(param + 5));
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ret = omap_smc3(idx, process, flag, __pa(param));
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flush_cache_all();
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local_fiq_enable();
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local_irq_enable();
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return ret;
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}
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/**
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* rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
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* @set_bits: bits to set in ACR
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* @clr_bits: bits to clear in ACR
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*
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* Return the non-zero error value on failure.
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*/
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u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
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0,
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FLAG_START_CRITICAL,
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1, acr, 0, 0, 0);
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}
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/**
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* rx51_secure_rng_call: Routine for HW random generator
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*/
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u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
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{
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return rx51_secure_dispatcher(RX51_PPA_HWRNG,
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0,
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NO_FLAG,
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3, ptr, count, flag, 0);
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}
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