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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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225c7b1fee
Add an InfiniBand driver for Mellanox ConnectX adapters. Because
these adapters can also be used as ethernet NICs and Fibre Channel
HBAs, the driver is split into two modules:
mlx4_core: Handles low-level things like device initialization and
processing firmware commands. Also controls resource allocation
so that the InfiniBand, ethernet and FC functions can share a
device without stepping on each other.
mlx4_ib: Handles InfiniBand-specific things; plugs into the
InfiniBand midlayer.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
281 lines
8.1 KiB
C
281 lines
8.1 KiB
C
/*
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* Copyright (c) 2004 Topspin Communications. All rights reserved.
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* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/init.h>
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#include <linux/mlx4/cmd.h>
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#include <linux/mlx4/qp.h>
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#include "mlx4.h"
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#include "icm.h"
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void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
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{
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struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
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struct mlx4_qp *qp;
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spin_lock(&qp_table->lock);
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qp = __mlx4_qp_lookup(dev, qpn);
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if (qp)
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atomic_inc(&qp->refcount);
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spin_unlock(&qp_table->lock);
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if (!qp) {
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mlx4_warn(dev, "Async event for bogus QP %08x\n", qpn);
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return;
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}
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qp->event(qp, event_type);
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if (atomic_dec_and_test(&qp->refcount))
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complete(&qp->free);
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}
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int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
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enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
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struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
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int sqd_event, struct mlx4_qp *qp)
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{
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static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
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[MLX4_QP_STATE_RST] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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[MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP,
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},
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[MLX4_QP_STATE_INIT] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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[MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP,
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[MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP,
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},
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[MLX4_QP_STATE_RTR] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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[MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP,
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},
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[MLX4_QP_STATE_RTS] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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[MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP,
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[MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP,
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},
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[MLX4_QP_STATE_SQD] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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[MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP,
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[MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP,
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},
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[MLX4_QP_STATE_SQER] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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[MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP,
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},
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[MLX4_QP_STATE_ERR] = {
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[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
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[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
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}
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};
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struct mlx4_cmd_mailbox *mailbox;
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int ret = 0;
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if (cur_state < 0 || cur_state >= MLX4_QP_NUM_STATE ||
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new_state < 0 || cur_state >= MLX4_QP_NUM_STATE ||
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!op[cur_state][new_state])
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return -EINVAL;
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if (op[cur_state][new_state] == MLX4_CMD_2RST_QP)
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return mlx4_cmd(dev, 0, qp->qpn, 2,
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MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A);
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
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u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
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context->mtt_base_addr_h = mtt_addr >> 32;
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context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
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context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
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}
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*(__be32 *) mailbox->buf = cpu_to_be32(optpar);
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memcpy(mailbox->buf + 8, context, sizeof *context);
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((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
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cpu_to_be32(qp->qpn);
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ret = mlx4_cmd(dev, mailbox->dma, qp->qpn | (!!sqd_event << 31),
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new_state == MLX4_QP_STATE_RST ? 2 : 0,
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op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return ret;
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}
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EXPORT_SYMBOL_GPL(mlx4_qp_modify);
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int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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struct mlx4_qp_table *qp_table = &priv->qp_table;
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int err;
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if (sqpn)
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qp->qpn = sqpn;
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else {
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qp->qpn = mlx4_bitmap_alloc(&qp_table->bitmap);
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if (qp->qpn == -1)
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return -ENOMEM;
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}
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err = mlx4_table_get(dev, &qp_table->qp_table, qp->qpn);
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if (err)
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goto err_out;
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err = mlx4_table_get(dev, &qp_table->auxc_table, qp->qpn);
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if (err)
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goto err_put_qp;
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err = mlx4_table_get(dev, &qp_table->altc_table, qp->qpn);
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if (err)
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goto err_put_auxc;
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err = mlx4_table_get(dev, &qp_table->rdmarc_table, qp->qpn);
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if (err)
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goto err_put_altc;
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err = mlx4_table_get(dev, &qp_table->cmpt_table, qp->qpn);
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if (err)
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goto err_put_rdmarc;
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spin_lock_irq(&qp_table->lock);
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err = radix_tree_insert(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1), qp);
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spin_unlock_irq(&qp_table->lock);
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if (err)
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goto err_put_cmpt;
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atomic_set(&qp->refcount, 1);
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init_completion(&qp->free);
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return 0;
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err_put_cmpt:
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mlx4_table_put(dev, &qp_table->cmpt_table, qp->qpn);
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err_put_rdmarc:
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mlx4_table_put(dev, &qp_table->rdmarc_table, qp->qpn);
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err_put_altc:
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mlx4_table_put(dev, &qp_table->altc_table, qp->qpn);
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err_put_auxc:
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mlx4_table_put(dev, &qp_table->auxc_table, qp->qpn);
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err_put_qp:
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mlx4_table_put(dev, &qp_table->qp_table, qp->qpn);
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err_out:
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if (!sqpn)
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mlx4_bitmap_free(&qp_table->bitmap, qp->qpn);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
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void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
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{
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struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
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unsigned long flags;
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spin_lock_irqsave(&qp_table->lock, flags);
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radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
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spin_unlock_irqrestore(&qp_table->lock, flags);
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}
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EXPORT_SYMBOL_GPL(mlx4_qp_remove);
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void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
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{
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struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
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if (atomic_dec_and_test(&qp->refcount))
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complete(&qp->free);
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wait_for_completion(&qp->free);
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mlx4_table_put(dev, &qp_table->cmpt_table, qp->qpn);
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mlx4_table_put(dev, &qp_table->rdmarc_table, qp->qpn);
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mlx4_table_put(dev, &qp_table->altc_table, qp->qpn);
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mlx4_table_put(dev, &qp_table->auxc_table, qp->qpn);
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mlx4_table_put(dev, &qp_table->qp_table, qp->qpn);
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mlx4_bitmap_free(&qp_table->bitmap, qp->qpn);
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}
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EXPORT_SYMBOL_GPL(mlx4_qp_free);
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static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
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{
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return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
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MLX4_CMD_TIME_CLASS_B);
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}
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int __devinit mlx4_init_qp_table(struct mlx4_dev *dev)
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{
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struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
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int err;
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spin_lock_init(&qp_table->lock);
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INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
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/*
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* We reserve 2 extra QPs per port for the special QPs. The
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* block of special QPs must be aligned to a multiple of 8, so
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* round up.
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*/
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dev->caps.sqp_start = ALIGN(dev->caps.reserved_qps, 8);
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err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps,
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(1 << 24) - 1, dev->caps.sqp_start + 8);
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if (err)
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return err;
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return mlx4_CONF_SPECIAL_QP(dev, dev->caps.sqp_start);
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}
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void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
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{
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mlx4_CONF_SPECIAL_QP(dev, 0);
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mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap);
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}
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