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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 09:06:44 +07:00
3cbd6a6ca8
Until now only one Armada XP and one Armada 388 based board supported suspend to ram. However, most of the recent mvebu SoCs can support the standby mode. Unlike for the suspend to ram, nothing special has to be done for these SoCs. This patch allows the system to use the standby mode on Armada 370, 38x, 39x and XP SoCs. There are issues with the Armada 375, and the support might be added (if possible) in a future patch. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
153 lines
3.4 KiB
C
153 lines
3.4 KiB
C
/*
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* Board-level suspend/resume support.
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*
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* Copyright (C) 2014-2015 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/slab.h>
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#include "common.h"
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#define ARMADA_PIC_NR_GPIOS 3
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static void __iomem *gpio_ctrl;
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static int pic_gpios[ARMADA_PIC_NR_GPIOS];
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static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
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static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
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{
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u32 reg, ackcmd;
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int i;
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/* Put 001 as value on the GPIOs */
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reg = readl(gpio_ctrl);
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for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
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reg &= ~BIT(pic_raw_gpios[i]);
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reg |= BIT(pic_raw_gpios[0]);
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writel(reg, gpio_ctrl);
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/* Prepare writing 111 to the GPIOs */
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ackcmd = readl(gpio_ctrl);
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for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
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ackcmd |= BIT(pic_raw_gpios[i]);
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srcmd = cpu_to_le32(srcmd);
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ackcmd = cpu_to_le32(ackcmd);
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/*
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* Wait a while, the PIC needs quite a bit of time between the
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* two GPIO commands.
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*/
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mdelay(3000);
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asm volatile (
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/* Align to a cache line */
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".balign 32\n\t"
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/* Enter self refresh */
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"str %[srcmd], [%[sdram_reg]]\n\t"
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/*
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* Wait 100 cycles for DDR to enter self refresh, by
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* doing 50 times two instructions.
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*/
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"mov r1, #50\n\t"
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"1: subs r1, r1, #1\n\t"
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"bne 1b\n\t"
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/* Issue the command ACK */
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"str %[ackcmd], [%[gpio_ctrl]]\n\t"
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/* Trap the processor */
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"b .\n\t"
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: : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg),
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[ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
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}
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static int __init mvebu_armada_pm_init(void)
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{
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struct device_node *np;
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struct device_node *gpio_ctrl_np;
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int ret = 0, i;
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if (!of_machine_is_compatible("marvell,axp-gp"))
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return -ENODEV;
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np = of_find_node_by_name(NULL, "pm_pic");
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if (!np)
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return -ENODEV;
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for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
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char *name;
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struct of_phandle_args args;
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pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i);
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if (pic_gpios[i] < 0) {
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ret = -ENODEV;
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goto out;
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}
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name = kasprintf(GFP_KERNEL, "pic-pin%d", i);
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if (!name) {
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ret = -ENOMEM;
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goto out;
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}
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ret = gpio_request(pic_gpios[i], name);
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if (ret < 0) {
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kfree(name);
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goto out;
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}
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ret = gpio_direction_output(pic_gpios[i], 0);
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if (ret < 0) {
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gpio_free(pic_gpios[i]);
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kfree(name);
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goto out;
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}
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ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2,
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i, &args);
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if (ret < 0) {
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gpio_free(pic_gpios[i]);
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kfree(name);
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goto out;
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}
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gpio_ctrl_np = args.np;
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pic_raw_gpios[i] = args.args[0];
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}
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gpio_ctrl = of_iomap(gpio_ctrl_np, 0);
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if (!gpio_ctrl)
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return -ENOMEM;
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mvebu_pm_suspend_init(mvebu_armada_pm_enter);
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out:
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of_node_put(np);
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return ret;
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}
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/*
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* Registering the mvebu_board_pm_enter callback must be done before
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* the platform_suspend_ops will be registered. In the same time we
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* also need to have the gpio devices registered. That's why we use a
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* device_initcall_sync which is called after all the device_initcall
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* (used by the gpio device) but before the late_initcall (used to
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* register the platform_suspend_ops)
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*/
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device_initcall_sync(mvebu_armada_pm_init);
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