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sve.rst describes a flag PR_SVE_SET_VL_INHERIT for the PR_SVE_SET_VL prctl, but there is no flag of this name. The flag is shared between the _GET and _SET calls, so the _SET prefix was dropped, giving the name PR_SVE_VL_INHERIT in the headers. Fix it. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Link: https://lore.kernel.org/r/1591808590-20210-2-git-send-email-Dave.Martin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
546 lines
20 KiB
ReStructuredText
546 lines
20 KiB
ReStructuredText
===================================================
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Scalable Vector Extension support for AArch64 Linux
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===================================================
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Author: Dave Martin <Dave.Martin@arm.com>
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Date: 4 August 2017
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This document outlines briefly the interface provided to userspace by Linux in
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order to support use of the ARM Scalable Vector Extension (SVE).
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This is an outline of the most important features and issues only and not
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intended to be exhaustive.
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This document does not aim to describe the SVE architecture or programmer's
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model. To aid understanding, a minimal description of relevant programmer's
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model features for SVE is included in Appendix A.
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1. General
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-----------
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* SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
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tracked per-thread.
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* The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
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AT_HWCAP entry. Presence of this flag implies the presence of the SVE
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instructions and registers, and the Linux-specific system interfaces
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described in this document. SVE is reported in /proc/cpuinfo as "sve".
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* Support for the execution of SVE instructions in userspace can also be
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detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
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instruction, and checking that the value of the SVE field is nonzero. [3]
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It does not guarantee the presence of the system interfaces described in the
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following sections: software that needs to verify that those interfaces are
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present must check for HWCAP_SVE instead.
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* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
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be reported in the AT_HWCAP2 aux vector entry. In addition to this,
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optional extensions to SVE2 may be reported by the presence of:
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HWCAP2_SVE2
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HWCAP2_SVEAES
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HWCAP2_SVEPMULL
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HWCAP2_SVEBITPERM
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HWCAP2_SVESHA3
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HWCAP2_SVESM4
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This list may be extended over time as the SVE architecture evolves.
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These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
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which userspace can read using an MRS instruction. See elf_hwcaps.txt and
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cpu-feature-registers.txt for details.
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* Debuggers should restrict themselves to interacting with the target via the
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NT_ARM_SVE regset. The recommended way of detecting support for this regset
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is to connect to a target process first and then attempt a
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ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).
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* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
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between userspace and the kernel, the register value is encoded in memory in
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an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
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byte offset i from the start of the memory representation. This affects for
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example the signal frame (struct sve_context) and ptrace interface
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(struct user_sve_header) and associated data.
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Beware that on big-endian systems this results in a different byte order than
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for the FPSIMD V-registers, which are stored as single host-endian 128-bit
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values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
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byte offset i. (struct fpsimd_context, struct user_fpsimd_state).
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2. Vector length terminology
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-----------------------------
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The size of an SVE vector (Z) register is referred to as the "vector length".
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To avoid confusion about the units used to express vector length, the kernel
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adopts the following conventions:
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* Vector length (VL) = size of a Z-register in bytes
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* Vector quadwords (VQ) = size of a Z-register in units of 128 bits
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(So, VL = 16 * VQ.)
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The VQ convention is used where the underlying granularity is important, such
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as in data structure definitions. In most other situations, the VL convention
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is used. This is consistent with the meaning of the "VL" pseudo-register in
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the SVE instruction set architecture.
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3. System call behaviour
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-------------------------
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* On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] of
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Z0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFR
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become unspecified on return from a syscall.
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* The SVE registers are not used to pass arguments to or receive results from
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any syscall.
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* In practice the affected registers/bits will be preserved or will be replaced
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with zeros on return from a syscall, but userspace should not make
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assumptions about this. The kernel behaviour may vary on a case-by-case
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basis.
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* All other SVE state of a thread, including the currently configured vector
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length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
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length (if any), is preserved across all syscalls, subject to the specific
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exceptions for execve() described in section 6.
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In particular, on return from a fork() or clone(), the parent and new child
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process or thread share identical SVE configuration, matching that of the
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parent before the call.
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4. Signal handling
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-------------------
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* A new signal frame record sve_context encodes the SVE registers on signal
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delivery. [1]
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* This record is supplementary to fpsimd_context. The FPSR and FPCR registers
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are only present in fpsimd_context. For convenience, the content of V0..V31
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is duplicated between sve_context and fpsimd_context.
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* The signal frame record for SVE always contains basic metadata, in particular
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the thread's vector length (in sve_context.vl).
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* The SVE registers may or may not be included in the record, depending on
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whether the registers are live for the thread. The registers are present if
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and only if:
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sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).
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* If the registers are present, the remainder of the record has a vl-dependent
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size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to
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the members.
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* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
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layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
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start of the register's representation in memory.
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* If the SVE context is too big to fit in sigcontext.__reserved[], then extra
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space is allocated on the stack, an extra_context record is written in
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__reserved[] referencing this space. sve_context is then written in the
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extra space. Refer to [1] for further details about this mechanism.
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5. Signal return
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-----------------
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When returning from a signal handler:
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* If there is no sve_context record in the signal frame, or if the record is
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present but contains no register data as desribed in the previous section,
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then the SVE registers/bits become non-live and take unspecified values.
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* If sve_context is present in the signal frame and contains full register
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data, the SVE registers become live and are populated with the specified
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data. However, for backward compatibility reasons, bits [127:0] of Z0..Z31
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are always restored from the corresponding members of fpsimd_context.vregs[]
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and not from sve_context. The remaining bits are restored from sve_context.
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* Inclusion of fpsimd_context in the signal frame remains mandatory,
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irrespective of whether sve_context is present or not.
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* The vector length cannot be changed via signal return. If sve_context.vl in
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the signal frame does not match the current vector length, the signal return
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attempt is treated as illegal, resulting in a forced SIGSEGV.
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6. prctl extensions
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--------------------
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Some new prctl() calls are added to allow programs to manage the SVE vector
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length:
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prctl(PR_SVE_SET_VL, unsigned long arg)
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Sets the vector length of the calling thread and related flags, where
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arg == vl | flags. Other threads of the calling process are unaffected.
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vl is the desired vector length, where sve_vl_valid(vl) must be true.
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flags:
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PR_SVE_VL_INHERIT
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Inherit the current vector length across execve(). Otherwise, the
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vector length is reset to the system default at execve(). (See
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Section 9.)
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PR_SVE_SET_VL_ONEXEC
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Defer the requested vector length change until the next execve()
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performed by this thread.
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The effect is equivalent to implicit exceution of the following
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call immediately after the next execve() (if any) by the thread:
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prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
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This allows launching of a new program with a different vector
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length, while avoiding runtime side effects in the caller.
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Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
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immediately.
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Return value: a nonnegative on success, or a negative value on error:
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EINVAL: SVE not supported, invalid vector length requested, or
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invalid flags.
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On success:
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* Either the calling thread's vector length or the deferred vector length
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to be applied at the next execve() by the thread (dependent on whether
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PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
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supported by the system that is less than or equal to vl. If vl ==
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SVE_VL_MAX, the value set will be the largest value supported by the
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system.
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* Any previously outstanding deferred vector length change in the calling
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thread is cancelled.
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* The returned value describes the resulting configuration, encoded as for
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PR_SVE_GET_VL. The vector length reported in this value is the new
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current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
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present in arg; otherwise, the reported vector length is the deferred
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vector length that will be applied at the next execve() by the calling
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thread.
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* Changing the vector length causes all of P0..P15, FFR and all bits of
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Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
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unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current
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vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
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flag, does not constitute a change to the vector length for this purpose.
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prctl(PR_SVE_GET_VL)
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Gets the vector length of the calling thread.
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The following flag may be OR-ed into the result:
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PR_SVE_VL_INHERIT
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Vector length will be inherited across execve().
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There is no way to determine whether there is an outstanding deferred
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vector length change (which would only normally be the case between a
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fork() or vfork() and the corresponding execve() in typical use).
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To extract the vector length from the result, and it with
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PR_SVE_VL_LEN_MASK.
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Return value: a nonnegative value on success, or a negative value on error:
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EINVAL: SVE not supported.
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7. ptrace extensions
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---------------------
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* A new regset NT_ARM_SVE is defined for use with PTRACE_GETREGSET and
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PTRACE_SETREGSET.
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Refer to [2] for definitions.
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The regset data starts with struct user_sve_header, containing:
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size
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Size of the complete regset, in bytes.
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This depends on vl and possibly on other things in the future.
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If a call to PTRACE_GETREGSET requests less data than the value of
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size, the caller can allocate a larger buffer and retry in order to
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read the complete regset.
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max_size
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Maximum size in bytes that the regset can grow to for the target
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thread. The regset won't grow bigger than this even if the target
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thread changes its vector length etc.
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vl
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Target thread's current vector length, in bytes.
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max_vl
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Maximum possible vector length for the target thread.
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flags
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either
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SVE_PT_REGS_FPSIMD
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SVE registers are not live (GETREGSET) or are to be made
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non-live (SETREGSET).
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The payload is of type struct user_fpsimd_state, with the same
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meaning as for NT_PRFPREG, starting at offset
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SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.
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Extra data might be appended in the future: the size of the
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payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).
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vq should be obtained using sve_vq_from_vl(vl).
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or
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SVE_PT_REGS_SVE
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SVE registers are live (GETREGSET) or are to be made live
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(SETREGSET).
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The payload contains the SVE register data, starting at offset
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SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
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size SVE_PT_SVE_SIZE(vq, flags);
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... OR-ed with zero or more of the following flags, which have the same
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meaning and behaviour as the corresponding PR_SET_VL_* flags:
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SVE_PT_VL_INHERIT
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SVE_PT_VL_ONEXEC (SETREGSET only).
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* The effects of changing the vector length and/or flags are equivalent to
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those documented for PR_SVE_SET_VL.
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The caller must make a further GETREGSET call if it needs to know what VL is
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actually set by SETREGSET, unless is it known in advance that the requested
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VL is supported.
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* In the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
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the header fields. The SVE_PT_SVE_*() macros are provided to facilitate
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access to the members.
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* In either case, for SETREGSET it is permissible to omit the payload, in which
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case only the vector length and flags are changed (along with any
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consequences of those changes).
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* For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
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requested VL is not supported, the effect will be the same as if the
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payload were omitted, except that an EIO error is reported. No
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attempt is made to translate the payload data to the correct layout
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for the vector length actually set. The thread's FPSIMD state is
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preserved, but the remaining bits of the SVE registers become
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unspecified. It is up to the caller to translate the payload layout
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for the actual VL and retry.
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* The effect of writing a partial, incomplete payload is unspecified.
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8. ELF coredump extensions
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---------------------------
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* A NT_ARM_SVE note will be added to each coredump for each thread of the
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dumped process. The contents will be equivalent to the data that would have
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been read if a PTRACE_GETREGSET of NT_ARM_SVE were executed for each thread
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when the coredump was generated.
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9. System runtime configuration
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--------------------------------
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* To mitigate the ABI impact of expansion of the signal frame, a policy
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mechanism is provided for administrators, distro maintainers and developers
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to set the default vector length for userspace processes:
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/proc/sys/abi/sve_default_vector_length
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Writing the text representation of an integer to this file sets the system
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default vector length to the specified value, unless the value is greater
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than the maximum vector length supported by the system in which case the
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default vector length is set to that maximum.
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The result can be determined by reopening the file and reading its
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contents.
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At boot, the default vector length is initially set to 64 or the maximum
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supported vector length, whichever is smaller. This determines the initial
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vector length of the init process (PID 1).
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Reading this file returns the current system default vector length.
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* At every execve() call, the new vector length of the new process is set to
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the system default vector length, unless
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* PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
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calling thread, or
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* a deferred vector length change is pending, established via the
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PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
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* Modifying the system default vector length does not affect the vector length
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of any existing process or thread that does not make an execve() call.
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Appendix A. SVE programmer's model (informative)
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=================================================
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This section provides a minimal description of the additions made by SVE to the
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ARMv8-A programmer's model that are relevant to this document.
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Note: This section is for information only and not intended to be complete or
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to replace any architectural specification.
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A.1. Registers
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---------------
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In A64 state, SVE adds the following:
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* 32 8VL-bit vector registers Z0..Z31
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For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
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A register write using a Vn register name zeros all bits of the corresponding
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Zn except for bits [127:0].
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* 16 VL-bit predicate registers P0..P15
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* 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
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* a VL "pseudo-register" that determines the size of each vector register
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The SVE instruction set architecture provides no way to write VL directly.
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Instead, it can be modified only by EL1 and above, by writing appropriate
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system registers.
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* The value of VL can be configured at runtime by EL1 and above:
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16 <= VL <= VLmax, where VL must be a multiple of 16.
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* The maximum vector length is determined by the hardware:
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16 <= VLmax <= 256.
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(The SVE architecture specifies 256, but permits future architecture
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revisions to raise this limit.)
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* FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
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operations in a similar way to the way in which they interact with ARMv8
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floating-point operations::
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8VL-1 128 0 bit index
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+---- //// -----------------+
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Z0 | : V0 |
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: :
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Z7 | : V7 |
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Z8 | : * V8 |
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: : :
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Z15 | : *V15 |
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Z16 | : V16 |
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: :
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Z31 | : V31 |
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+---- //// -----------------+
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31 0
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VL-1 0 +-------+
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+---- //// --+ FPSR | |
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P0 | | +-------+
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: | | *FPCR | |
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P15 | | +-------+
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+---- //// --+
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FFR | | +-----+
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+---- //// --+ VL | |
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+-----+
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(*) callee-save:
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This only applies to bits [63:0] of Z-/V-registers.
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FPCR contains callee-save and caller-save bits. See [4] for details.
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A.2. Procedure call standard
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-----------------------------
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The ARMv8-A base procedure call standard is extended as follows with respect to
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the additional SVE register state:
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* All SVE register bits that are not shared with FP/SIMD are caller-save.
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* Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.
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This follows from the way these bits are mapped to V8..V15, which are caller-
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save in the base procedure call standard.
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Appendix B. ARMv8-A FP/SIMD programmer's model
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===============================================
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Note: This section is for information only and not intended to be complete or
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to replace any architectural specification.
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Refer to [4] for for more information.
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ARMv8-A defines the following floating-point / SIMD register state:
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* 32 128-bit vector registers V0..V31
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* 2 32-bit status/control registers FPSR, FPCR
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::
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127 0 bit index
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+---------------+
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V0 | |
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: : :
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V7 | |
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* V8 | |
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: : : :
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*V15 | |
|
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V16 | |
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: : :
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|
V31 | |
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+---------------+
|
|
|
|
31 0
|
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+-------+
|
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FPSR | |
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+-------+
|
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*FPCR | |
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|
+-------+
|
|
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(*) callee-save:
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This only applies to bits [63:0] of V-registers.
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FPCR contains a mixture of callee-save and caller-save bits.
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|
|
|
|
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References
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|
==========
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[1] arch/arm64/include/uapi/asm/sigcontext.h
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AArch64 Linux signal ABI definitions
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|
|
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[2] arch/arm64/include/uapi/asm/ptrace.h
|
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AArch64 Linux ptrace ABI definitions
|
|
|
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[3] Documentation/arm64/cpu-feature-registers.rst
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|
|
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[4] ARM IHI0055C
|
|
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
|
|
http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
|
|
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
|