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797179bc4f
Copy __kvm_mips_vcpu_run() into unmapped memory, so that we can never get a TLB refill exception in it when KVM is built as a module. This was observed to happen with the host MIPS kernel running under QEMU, due to a not entirely transparent optimisation in the QEMU TLB handling where TLB entries replaced with TLBWR are copied to a separate part of the TLB array. Code in those pages continue to be executable, but those mappings persist only until the next ASID switch, even if they are marked global. An ASID switch happens in __kvm_mips_vcpu_run() at exception level after switching to the guest exception base. Subsequent TLB mapped kernel instructions just prior to switching to the guest trigger a TLB refill exception, which enters the guest exception handlers without updating EPC. This appears as a guest triggered TLB refill on a host kernel mapped (host KSeg2) address, which is not handled correctly as user (guest) mode accesses to kernel (host) segments always generate address error exceptions. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.10.x- Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
55 lines
2.0 KiB
C
55 lines
2.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS: Interrupts
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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/*
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* MIPS Exception Priorities, exceptions (including interrupts) are queued up
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* for the guest in the order specified by their priorities
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*/
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#define MIPS_EXC_RESET 0
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#define MIPS_EXC_SRESET 1
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#define MIPS_EXC_DEBUG_ST 2
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#define MIPS_EXC_DEBUG 3
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#define MIPS_EXC_DDB 4
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#define MIPS_EXC_NMI 5
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#define MIPS_EXC_MCHK 6
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#define MIPS_EXC_INT_TIMER 7
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#define MIPS_EXC_INT_IO 8
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#define MIPS_EXC_EXECUTE 9
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#define MIPS_EXC_INT_IPI_1 10
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#define MIPS_EXC_INT_IPI_2 11
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#define MIPS_EXC_MAX 12
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/* XXXSL More to follow */
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extern char __kvm_mips_vcpu_run_end[];
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extern char mips32_exception[], mips32_exceptionEnd[];
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extern char mips32_GuestException[], mips32_GuestExceptionEnd[];
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#define C_TI (_ULCAST_(1) << 30)
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#define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (0)
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#define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (0)
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void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, uint32_t priority);
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void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, uint32_t priority);
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int kvm_mips_pending_timer(struct kvm_vcpu *vcpu);
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void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu);
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void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu);
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void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
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struct kvm_mips_interrupt *irq);
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void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
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struct kvm_mips_interrupt *irq);
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int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
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uint32_t cause);
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int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
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uint32_t cause);
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void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, uint32_t cause);
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