mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 11:20:49 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
219 lines
7.4 KiB
C
219 lines
7.4 KiB
C
#ifndef FEC_8XX_H
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#define FEC_8XX_H
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#include <linux/mii.h>
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#include <linux/netdevice.h>
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#include <linux/types.h>
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/* HW info */
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/* CRC polynomium used by the FEC for the multicast group filtering */
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#define FEC_CRC_POLY 0x04C11DB7
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#define MII_ADVERTISE_HALF (ADVERTISE_100HALF | \
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ADVERTISE_10HALF | ADVERTISE_CSMA)
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#define MII_ADVERTISE_ALL (ADVERTISE_100FULL | \
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ADVERTISE_10FULL | MII_ADVERTISE_HALF)
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/* Interrupt events/masks.
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*/
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#define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
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#define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
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#define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
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#define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
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#define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
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#define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
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#define FEC_ENET_RXF 0x02000000U /* Full frame received */
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#define FEC_ENET_RXB 0x01000000U /* A buffer was received */
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#define FEC_ENET_MII 0x00800000U /* MII interrupt */
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#define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
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#define FEC_ECNTRL_PINMUX 0x00000004
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#define FEC_ECNTRL_ETHER_EN 0x00000002
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#define FEC_ECNTRL_RESET 0x00000001
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#define FEC_RCNTRL_BC_REJ 0x00000010
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#define FEC_RCNTRL_PROM 0x00000008
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#define FEC_RCNTRL_MII_MODE 0x00000004
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#define FEC_RCNTRL_DRT 0x00000002
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#define FEC_RCNTRL_LOOP 0x00000001
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#define FEC_TCNTRL_FDEN 0x00000004
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#define FEC_TCNTRL_HBC 0x00000002
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#define FEC_TCNTRL_GTS 0x00000001
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/* values for MII phy_status */
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#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
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#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
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#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
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#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
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#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
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#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
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#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
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#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
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#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
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#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
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#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
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#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
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#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
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#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
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#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
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typedef struct phy_info {
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unsigned int id;
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const char *name;
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void (*startup) (struct net_device * dev);
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void (*shutdown) (struct net_device * dev);
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void (*ack_int) (struct net_device * dev);
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} phy_info_t;
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/* The FEC stores dest/src/type, data, and checksum for receive packets.
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*/
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#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */
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#define MIN_MTU 46 /* this is data size */
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#define CRC_LEN 4
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#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN)
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#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN)
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/* Must be a multiple of 4 */
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#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE+3) & ~3)
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/* This is needed so that invalidate_xxx wont invalidate too much */
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#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE)
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/* platform interface */
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struct fec_platform_info {
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int fec_no; /* FEC index */
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int use_mdio; /* use external MII */
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int phy_addr; /* the phy address */
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int fec_irq, phy_irq; /* the irq for the controller */
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int rx_ring, tx_ring; /* number of buffers on rx */
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int sys_clk; /* system clock */
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__u8 macaddr[6]; /* mac address */
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int rx_copybreak; /* limit we copy small frames */
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int use_napi; /* use NAPI */
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int napi_weight; /* NAPI weight */
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};
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/* forward declaration */
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struct fec;
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struct fec_enet_private {
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spinlock_t lock; /* during all ops except TX pckt processing */
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spinlock_t tx_lock; /* during fec_start_xmit and fec_tx */
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int fecno;
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struct fec *fecp;
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const struct fec_platform_info *fpi;
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int rx_ring, tx_ring;
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dma_addr_t ring_mem_addr;
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void *ring_base;
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struct sk_buff **rx_skbuff;
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struct sk_buff **tx_skbuff;
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cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
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cbd_t *tx_bd_base;
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cbd_t *dirty_tx; /* ring entries to be free()ed. */
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cbd_t *cur_rx;
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cbd_t *cur_tx;
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int tx_free;
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struct net_device_stats stats;
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struct timer_list phy_timer_list;
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const struct phy_info *phy;
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unsigned int fec_phy_speed;
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__u32 msg_enable;
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struct mii_if_info mii_if;
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};
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/***************************************************************************/
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void fec_restart(struct net_device *dev, int duplex, int speed);
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void fec_stop(struct net_device *dev);
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/***************************************************************************/
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int fec_mii_read(struct net_device *dev, int phy_id, int location);
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void fec_mii_write(struct net_device *dev, int phy_id, int location, int value);
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int fec_mii_phy_id_detect(struct net_device *dev);
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void fec_mii_startup(struct net_device *dev);
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void fec_mii_shutdown(struct net_device *dev);
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void fec_mii_ack_int(struct net_device *dev);
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void fec_mii_link_status_change_check(struct net_device *dev, int init_media);
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/***************************************************************************/
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#define FEC1_NO 0x00
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#define FEC2_NO 0x01
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#define FEC3_NO 0x02
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int fec_8xx_init_one(const struct fec_platform_info *fpi,
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struct net_device **devp);
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int fec_8xx_cleanup_one(struct net_device *dev);
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/***************************************************************************/
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#define DRV_MODULE_NAME "fec_8xx"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "0.1"
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#define DRV_MODULE_RELDATE "May 6, 2004"
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/***************************************************************************/
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int fec_8xx_platform_init(void);
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void fec_8xx_platform_cleanup(void);
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/***************************************************************************/
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/* FEC access macros */
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#if defined(CONFIG_8xx)
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/* for a 8xx __raw_xxx's are sufficient */
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#define __fec_out32(addr, x) __raw_writel(x, addr)
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#define __fec_out16(addr, x) __raw_writew(x, addr)
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#define __fec_in32(addr) __raw_readl(addr)
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#define __fec_in16(addr) __raw_readw(addr)
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#else
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/* for others play it safe */
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#define __fec_out32(addr, x) out_be32(addr, x)
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#define __fec_out16(addr, x) out_be16(addr, x)
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#define __fec_in32(addr) in_be32(addr)
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#define __fec_in16(addr) in_be16(addr)
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#endif
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/* write */
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#define FW(_fecp, _reg, _v) __fec_out32(&(_fecp)->fec_ ## _reg, (_v))
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/* read */
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#define FR(_fecp, _reg) __fec_in32(&(_fecp)->fec_ ## _reg)
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/* set bits */
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#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
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/* clear bits */
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#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
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/* buffer descriptor access macros */
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/* write */
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#define CBDW_SC(_cbd, _sc) __fec_out16(&(_cbd)->cbd_sc, (_sc))
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#define CBDW_DATLEN(_cbd, _datlen) __fec_out16(&(_cbd)->cbd_datlen, (_datlen))
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#define CBDW_BUFADDR(_cbd, _bufaddr) __fec_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
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/* read */
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#define CBDR_SC(_cbd) __fec_in16(&(_cbd)->cbd_sc)
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#define CBDR_DATLEN(_cbd) __fec_in16(&(_cbd)->cbd_datlen)
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#define CBDR_BUFADDR(_cbd) __fec_in32(&(_cbd)->cbd_bufaddr)
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/* set bits */
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#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
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/* clear bits */
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#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
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/***************************************************************************/
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#endif
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