mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 23:16:34 +07:00
9ed68785f7
[Needed for HSDK]
Currently the first page of system (hence RAM base) is assumed to be
@ CONFIG_LINUX_LINK_BASE, where kernel itself is linked.
However is case of HSDK platform, for reasons explained in that patch,
this is not true. kernel needs to be linked @ 0x9000_0000 while DDR
is still wired at 0x8000_0000. To properly account for this 256M of RAM,
we need to introduce a new option and base page frame accountiing off of
it.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: renamed CONFIG_KERNEL_RAM_BASE_ADDRESS => CONFIG_LINUX_RAM_BASE
: simplified changelog]
71 lines
1.5 KiB
Plaintext
71 lines
1.5 KiB
Plaintext
/*
|
|
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
/include/ "skeleton_hs.dtsi"
|
|
|
|
/ {
|
|
model = "snps,nsim_hs";
|
|
compatible = "snps,nsim_hs";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&core_intc>;
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
|
|
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
|
|
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
|
|
};
|
|
|
|
aliases {
|
|
serial0 = &arcuart0;
|
|
};
|
|
|
|
fpga {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* only perip space at end of low mem accessible
|
|
bus addr, parent bus addr, size */
|
|
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
|
|
|
|
core_clk: core_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <80000000>;
|
|
};
|
|
|
|
core_intc: core-interrupt-controller {
|
|
compatible = "snps,archs-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
arcuart0: serial@c0fc1000 {
|
|
compatible = "snps,arc-uart";
|
|
reg = <0xc0fc1000 0x100>;
|
|
interrupts = <24>;
|
|
clock-frequency = <80000000>;
|
|
current-speed = <115200>;
|
|
status = "okay";
|
|
};
|
|
|
|
arcpct0: pct {
|
|
compatible = "snps,archs-pct";
|
|
#interrupt-cells = <1>;
|
|
interrupts = <20>;
|
|
};
|
|
};
|
|
};
|