mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 05:38:29 +07:00
9948a0641a
Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
574 lines
15 KiB
C
574 lines
15 KiB
C
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/skbuff.h>
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#include <linux/if_vlan.h>
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#include <net/switchdev.h>
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#include "pci.h"
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#include "core.h"
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#include "reg.h"
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#include "port.h"
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#include "trap.h"
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#include "txheader.h"
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#include "ib.h"
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static const char mlxsw_sib_driver_name[] = "mlxsw_switchib";
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static const char mlxsw_sib2_driver_name[] = "mlxsw_switchib2";
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struct mlxsw_sib_port;
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struct mlxsw_sib {
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struct mlxsw_sib_port **ports;
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struct mlxsw_core *core;
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const struct mlxsw_bus_info *bus_info;
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};
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struct mlxsw_sib_port {
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struct mlxsw_sib *mlxsw_sib;
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u8 local_port;
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struct {
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u8 module;
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} mapping;
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};
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/* tx_v1_hdr_version
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* Tx header version.
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* Must be set to 1.
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*/
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MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4);
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/* tx_v1_hdr_ctl
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* Packet control type.
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* 0 - Ethernet control (e.g. EMADs, LACP)
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* 1 - Ethernet data
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*/
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MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2);
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/* tx_v1_hdr_proto
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* Packet protocol type. Must be set to 1 (Ethernet).
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*/
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MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3);
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/* tx_v1_hdr_swid
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* Switch partition ID. Must be set to 0.
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*/
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MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3);
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/* tx_v1_hdr_control_tclass
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* Indicates if the packet should use the control TClass and not one
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* of the data TClasses.
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*/
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MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1);
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/* tx_v1_hdr_port_mid
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* Destination local port for unicast packets.
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* Destination multicast ID for multicast packets.
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*
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* Control packets are directed to a specific egress port, while data
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* packets are transmitted through the CPU port (0) into the switch partition,
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* where forwarding rules are applied.
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*/
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MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16);
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/* tx_v1_hdr_type
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* 0 - Data packets
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* 6 - Control packets
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*/
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MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4);
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static void
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mlxsw_sib_tx_v1_hdr_construct(struct sk_buff *skb,
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const struct mlxsw_tx_info *tx_info)
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{
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char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
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memset(txhdr, 0, MLXSW_TXHDR_LEN);
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mlxsw_tx_v1_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
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mlxsw_tx_v1_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
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mlxsw_tx_v1_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
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mlxsw_tx_v1_hdr_swid_set(txhdr, 0);
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mlxsw_tx_v1_hdr_control_tclass_set(txhdr, 1);
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mlxsw_tx_v1_hdr_port_mid_set(txhdr, tx_info->local_port);
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mlxsw_tx_v1_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
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}
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static int
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mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port *mlxsw_sib_port,
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bool is_up)
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{
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struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
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char paos_pl[MLXSW_REG_PAOS_LEN];
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mlxsw_reg_paos_pack(paos_pl, mlxsw_sib_port->local_port,
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is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
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MLXSW_PORT_ADMIN_STATUS_DOWN);
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return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(paos), paos_pl);
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}
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static int mlxsw_sib_port_mtu_set(struct mlxsw_sib_port *mlxsw_sib_port,
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u16 mtu)
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{
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struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
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char pmtu_pl[MLXSW_REG_PMTU_LEN];
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int max_mtu;
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int err;
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mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, 0);
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err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
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if (err)
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return err;
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max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
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if (mtu > max_mtu)
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return -EINVAL;
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mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, mtu);
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return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
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}
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static int mlxsw_sib_port_set(struct mlxsw_sib_port *mlxsw_sib_port, u8 port)
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{
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struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
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char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
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int err;
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mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sib_port->local_port);
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mlxsw_reg_plib_ib_port_set(plib_pl, port);
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err = mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(plib), plib_pl);
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return err;
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}
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static int mlxsw_sib_port_swid_set(struct mlxsw_sib_port *mlxsw_sib_port,
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u8 swid)
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{
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struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
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char pspa_pl[MLXSW_REG_PSPA_LEN];
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mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sib_port->local_port);
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return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pspa), pspa_pl);
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}
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static int mlxsw_sib_port_module_info_get(struct mlxsw_sib *mlxsw_sib,
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u8 local_port, u8 *p_module,
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u8 *p_width)
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{
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char pmlp_pl[MLXSW_REG_PMLP_LEN];
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int err;
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mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
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err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmlp), pmlp_pl);
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if (err)
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return err;
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*p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
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*p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
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return 0;
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}
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static int mlxsw_sib_port_speed_set(struct mlxsw_sib_port *mlxsw_sib_port,
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u16 speed, u16 width)
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{
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struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
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char ptys_pl[MLXSW_REG_PTYS_LEN];
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mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sib_port->local_port, speed,
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width);
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return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(ptys), ptys_pl);
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}
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static bool mlxsw_sib_port_created(struct mlxsw_sib *mlxsw_sib, u8 local_port)
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{
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return mlxsw_sib->ports[local_port] != NULL;
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}
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static int __mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
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u8 module, u8 width)
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{
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struct mlxsw_sib_port *mlxsw_sib_port;
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int err;
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mlxsw_sib_port = kzalloc(sizeof(*mlxsw_sib_port), GFP_KERNEL);
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if (!mlxsw_sib_port)
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return -ENOMEM;
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mlxsw_sib_port->mlxsw_sib = mlxsw_sib;
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mlxsw_sib_port->local_port = local_port;
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mlxsw_sib_port->mapping.module = module;
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err = mlxsw_sib_port_swid_set(mlxsw_sib_port, 0);
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if (err) {
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dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set SWID\n",
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mlxsw_sib_port->local_port);
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goto err_port_swid_set;
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}
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/* Expose the IB port number as it's front panel name */
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err = mlxsw_sib_port_set(mlxsw_sib_port, module + 1);
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if (err) {
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dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set IB port\n",
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mlxsw_sib_port->local_port);
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goto err_port_ib_set;
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}
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/* Supports all speeds from SDR to FDR (bitmask) and support bus width
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* of 1x, 2x and 4x (3 bits bitmask)
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*/
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err = mlxsw_sib_port_speed_set(mlxsw_sib_port,
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MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
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BIT(3) - 1);
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if (err) {
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dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set speed\n",
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mlxsw_sib_port->local_port);
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goto err_port_speed_set;
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}
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/* Change to the maximum MTU the device supports, the SMA will take
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* care of the active MTU
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*/
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err = mlxsw_sib_port_mtu_set(mlxsw_sib_port, MLXSW_IB_DEFAULT_MTU);
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if (err) {
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dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set MTU\n",
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mlxsw_sib_port->local_port);
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goto err_port_mtu_set;
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}
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err = mlxsw_sib_port_admin_status_set(mlxsw_sib_port, true);
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if (err) {
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dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
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mlxsw_sib_port->local_port);
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goto err_port_admin_set;
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}
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mlxsw_core_port_ib_set(mlxsw_sib->core, mlxsw_sib_port->local_port,
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mlxsw_sib_port);
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mlxsw_sib->ports[local_port] = mlxsw_sib_port;
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return 0;
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err_port_admin_set:
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err_port_mtu_set:
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err_port_speed_set:
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err_port_ib_set:
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mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
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err_port_swid_set:
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kfree(mlxsw_sib_port);
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return err;
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}
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static int mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
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u8 module, u8 width)
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{
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int err;
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err = mlxsw_core_port_init(mlxsw_sib->core, local_port);
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if (err) {
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dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to init core port\n",
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local_port);
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return err;
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}
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err = __mlxsw_sib_port_create(mlxsw_sib, local_port, module, width);
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if (err)
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goto err_port_create;
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return 0;
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err_port_create:
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mlxsw_core_port_fini(mlxsw_sib->core, local_port);
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return err;
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}
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static void __mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
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{
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struct mlxsw_sib_port *mlxsw_sib_port = mlxsw_sib->ports[local_port];
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mlxsw_core_port_clear(mlxsw_sib->core, local_port, mlxsw_sib);
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mlxsw_sib->ports[local_port] = NULL;
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mlxsw_sib_port_admin_status_set(mlxsw_sib_port, false);
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mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
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kfree(mlxsw_sib_port);
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}
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static void mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
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{
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__mlxsw_sib_port_remove(mlxsw_sib, local_port);
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mlxsw_core_port_fini(mlxsw_sib->core, local_port);
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}
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static void mlxsw_sib_ports_remove(struct mlxsw_sib *mlxsw_sib)
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{
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int i;
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for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++)
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if (mlxsw_sib_port_created(mlxsw_sib, i))
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mlxsw_sib_port_remove(mlxsw_sib, i);
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kfree(mlxsw_sib->ports);
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}
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static int mlxsw_sib_ports_create(struct mlxsw_sib *mlxsw_sib)
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{
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size_t alloc_size;
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u8 module, width;
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int i;
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int err;
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alloc_size = sizeof(struct mlxsw_sib_port *) * MLXSW_PORT_MAX_IB_PORTS;
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mlxsw_sib->ports = kzalloc(alloc_size, GFP_KERNEL);
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if (!mlxsw_sib->ports)
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return -ENOMEM;
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for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) {
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err = mlxsw_sib_port_module_info_get(mlxsw_sib, i, &module,
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&width);
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if (err)
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goto err_port_module_info_get;
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if (!width)
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continue;
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err = mlxsw_sib_port_create(mlxsw_sib, i, module, width);
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if (err)
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goto err_port_create;
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}
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return 0;
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err_port_create:
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err_port_module_info_get:
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for (i--; i >= 1; i--)
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if (mlxsw_sib_port_created(mlxsw_sib, i))
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mlxsw_sib_port_remove(mlxsw_sib, i);
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kfree(mlxsw_sib->ports);
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return err;
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}
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static void
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mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port *mlxsw_sib_port,
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enum mlxsw_reg_pude_oper_status status)
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{
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if (status == MLXSW_PORT_OPER_STATUS_UP)
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pr_info("ib link for port %d - up\n",
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mlxsw_sib_port->mapping.module + 1);
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else
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pr_info("ib link for port %d - down\n",
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mlxsw_sib_port->mapping.module + 1);
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}
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static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg,
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char *pude_pl, void *priv)
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{
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struct mlxsw_sib *mlxsw_sib = priv;
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struct mlxsw_sib_port *mlxsw_sib_port;
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enum mlxsw_reg_pude_oper_status status;
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u8 local_port;
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local_port = mlxsw_reg_pude_local_port_get(pude_pl);
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mlxsw_sib_port = mlxsw_sib->ports[local_port];
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if (!mlxsw_sib_port) {
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dev_warn(mlxsw_sib->bus_info->dev, "Port %d: Link event received for non-existent port\n",
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local_port);
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return;
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}
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status = mlxsw_reg_pude_oper_status_get(pude_pl);
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mlxsw_sib_pude_ib_event_func(mlxsw_sib_port, status);
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}
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static const struct mlxsw_listener mlxsw_sib_listener[] = {
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MLXSW_EVENTL(mlxsw_sib_pude_event_func, PUDE, EMAD),
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};
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static int mlxsw_sib_taps_init(struct mlxsw_sib *mlxsw_sib)
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{
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int i;
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int err;
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for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
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err = mlxsw_core_trap_register(mlxsw_sib->core,
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&mlxsw_sib_listener[i],
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mlxsw_sib);
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if (err)
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goto err_rx_listener_register;
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}
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return 0;
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err_rx_listener_register:
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for (i--; i >= 0; i--) {
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mlxsw_core_trap_unregister(mlxsw_sib->core,
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&mlxsw_sib_listener[i],
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mlxsw_sib);
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}
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return err;
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}
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static void mlxsw_sib_traps_fini(struct mlxsw_sib *mlxsw_sib)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
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mlxsw_core_trap_unregister(mlxsw_sib->core,
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&mlxsw_sib_listener[i], mlxsw_sib);
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}
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}
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static int mlxsw_sib_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
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{
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char htgt_pl[MLXSW_REG_HTGT_LEN];
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mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
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MLXSW_REG_HTGT_INVALID_POLICER,
|
|
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
|
|
MLXSW_REG_HTGT_DEFAULT_TC);
|
|
mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
|
|
mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
|
|
MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD);
|
|
return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
|
|
}
|
|
|
|
static int mlxsw_sib_init(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_bus_info *mlxsw_bus_info)
|
|
{
|
|
struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
|
|
int err;
|
|
|
|
mlxsw_sib->core = mlxsw_core;
|
|
mlxsw_sib->bus_info = mlxsw_bus_info;
|
|
|
|
err = mlxsw_sib_ports_create(mlxsw_sib);
|
|
if (err) {
|
|
dev_err(mlxsw_sib->bus_info->dev, "Failed to create ports\n");
|
|
return err;
|
|
}
|
|
|
|
err = mlxsw_sib_taps_init(mlxsw_sib);
|
|
if (err) {
|
|
dev_err(mlxsw_sib->bus_info->dev, "Failed to set traps\n");
|
|
goto err_traps_init_err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_traps_init_err:
|
|
mlxsw_sib_ports_remove(mlxsw_sib);
|
|
return err;
|
|
}
|
|
|
|
static void mlxsw_sib_fini(struct mlxsw_core *mlxsw_core)
|
|
{
|
|
struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
mlxsw_sib_traps_fini(mlxsw_sib);
|
|
mlxsw_sib_ports_remove(mlxsw_sib);
|
|
}
|
|
|
|
static const struct mlxsw_config_profile mlxsw_sib_config_profile = {
|
|
.used_max_system_port = 1,
|
|
.max_system_port = 48000,
|
|
.used_max_ib_mc = 1,
|
|
.max_ib_mc = 27,
|
|
.used_max_pkey = 1,
|
|
.max_pkey = 32,
|
|
.swid_config = {
|
|
{
|
|
.used_type = 1,
|
|
.type = MLXSW_PORT_SWID_TYPE_IB,
|
|
}
|
|
},
|
|
};
|
|
|
|
static struct mlxsw_driver mlxsw_sib_driver = {
|
|
.kind = mlxsw_sib_driver_name,
|
|
.priv_size = sizeof(struct mlxsw_sib),
|
|
.init = mlxsw_sib_init,
|
|
.fini = mlxsw_sib_fini,
|
|
.basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
|
|
.txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
|
|
.txhdr_len = MLXSW_TXHDR_LEN,
|
|
.profile = &mlxsw_sib_config_profile,
|
|
};
|
|
|
|
static struct mlxsw_driver mlxsw_sib2_driver = {
|
|
.kind = mlxsw_sib2_driver_name,
|
|
.priv_size = sizeof(struct mlxsw_sib),
|
|
.init = mlxsw_sib_init,
|
|
.fini = mlxsw_sib_fini,
|
|
.basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
|
|
.txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
|
|
.txhdr_len = MLXSW_TXHDR_LEN,
|
|
.profile = &mlxsw_sib_config_profile,
|
|
};
|
|
|
|
static const struct pci_device_id mlxsw_sib_pci_id_table[] = {
|
|
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB), 0},
|
|
{0, },
|
|
};
|
|
|
|
static struct pci_driver mlxsw_sib_pci_driver = {
|
|
.name = mlxsw_sib_driver_name,
|
|
.id_table = mlxsw_sib_pci_id_table,
|
|
};
|
|
|
|
static const struct pci_device_id mlxsw_sib2_pci_id_table[] = {
|
|
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB2), 0},
|
|
{0, },
|
|
};
|
|
|
|
static struct pci_driver mlxsw_sib2_pci_driver = {
|
|
.name = mlxsw_sib2_driver_name,
|
|
.id_table = mlxsw_sib2_pci_id_table,
|
|
};
|
|
|
|
static int __init mlxsw_sib_module_init(void)
|
|
{
|
|
int err;
|
|
|
|
err = mlxsw_core_driver_register(&mlxsw_sib_driver);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mlxsw_core_driver_register(&mlxsw_sib2_driver);
|
|
if (err)
|
|
goto err_sib2_driver_register;
|
|
|
|
err = mlxsw_pci_driver_register(&mlxsw_sib_pci_driver);
|
|
if (err)
|
|
goto err_sib_pci_driver_register;
|
|
|
|
err = mlxsw_pci_driver_register(&mlxsw_sib2_pci_driver);
|
|
if (err)
|
|
goto err_sib2_pci_driver_register;
|
|
|
|
return 0;
|
|
|
|
err_sib2_pci_driver_register:
|
|
mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
|
|
err_sib_pci_driver_register:
|
|
mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
|
|
err_sib2_driver_register:
|
|
mlxsw_core_driver_unregister(&mlxsw_sib_driver);
|
|
return err;
|
|
}
|
|
|
|
static void __exit mlxsw_sib_module_exit(void)
|
|
{
|
|
mlxsw_pci_driver_unregister(&mlxsw_sib2_pci_driver);
|
|
mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
|
|
mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
|
|
mlxsw_core_driver_unregister(&mlxsw_sib_driver);
|
|
}
|
|
|
|
module_init(mlxsw_sib_module_init);
|
|
module_exit(mlxsw_sib_module_exit);
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_AUTHOR("Elad Raz <eladr@@mellanox.com>");
|
|
MODULE_DESCRIPTION("Mellanox SwitchIB and SwitchIB-2 driver");
|
|
MODULE_ALIAS("mlxsw_switchib2");
|
|
MODULE_DEVICE_TABLE(pci, mlxsw_sib_pci_id_table);
|
|
MODULE_DEVICE_TABLE(pci, mlxsw_sib2_pci_id_table);
|